1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # STMicroelectronics STM32MP13x (Single Cortex-A7)
4 # http://www.st.com/stm32mp1
6 # HLA does not support custom CSW nor AP other than 0
8 echo "ERROR: HLA transport cannot work with this target."
9 echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp13x_dk.cfg\"."
13 source [find target/swj-dp.tcl]
15 if { [info exists CHIPNAME] } {
16 set _CHIPNAME $CHIPNAME
18 set _CHIPNAME stm32mp13x
21 if { [info exists CPUTAPID] } {
22 set _CPUTAPID $CPUTAPID
25 set _CPUTAPID 0x6ba00477
27 set _CPUTAPID 0x6ba02477
31 # Chip Level TAP Controller, only in jtag mode
32 if { [info exists CLCTAPID] } {
33 set _CLCTAPID $CLCTAPID
35 set _CLCTAPID 0x06501041
38 swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
40 jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
43 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
45 # NOTE: keep ap-num and dbgbase to speed-up examine after reset
46 # NOTE: do not change the order of target create
47 target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
48 target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
49 target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
51 $_CHIPNAME.cpu cortex_a maskisr on
52 $_CHIPNAME.cpu cortex_a dacrfixup on
54 # interface does not work while srst is asserted
55 # this is target specific, valid for every board
56 # srst resets the debug unit, behavior equivalent to "srst_pulls_trst"
57 reset_config srst_gates_jtag srst_pulls_trst
60 adapter srst pulse_width 200
61 # bootrom has an internal timeout of 1 second for detecting the boot flash.
62 # wait at least 1 second to guarantee we are out of bootrom
63 adapter srst delay 1100
65 add_help_text axi_secure "Set secure mode for following AXI accesses"
67 $::_CHIPNAME.dap apsel 0
68 $::_CHIPNAME.dap apcsw 0x10006000
71 add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
73 $::_CHIPNAME.dap apsel 0
74 $::_CHIPNAME.dap apcsw 0x30006000
79 proc dbgmcu_enable_debug {} {
80 # keep clock enabled in low-power
81 ## catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
82 # freeze watchdog 1 and 2 on core halted
83 catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
84 catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
87 proc toggle_cpu_dbg_claim0 {} {
88 # toggle CPU0 DBG_CLAIM[0]
89 $::_CHIPNAME.ap1 mww 0xe00d0fa0 1
90 $::_CHIPNAME.ap1 mww 0xe00d0fa4 1
93 # FIXME: most of handlers below will be removed once reset framework get merged
94 $_CHIPNAME.ap1 configure -event reset-deassert-pre {
95 adapter deassert srst deassert trst
97 catch {$::_CHIPNAME.dap apid 1}
99 $_CHIPNAME.cpu configure -event reset-deassert-pre {$::_CHIPNAME.cpu arp_examine}
100 $_CHIPNAME.cpu configure -event reset-deassert-post {toggle_cpu_dbg_claim0; dbgmcu_enable_debug}
101 $_CHIPNAME.ap1 configure -event examine-start {dap init}
102 $_CHIPNAME.ap1 configure -event examine-end {dbgmcu_enable_debug}
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