tcl/target/stm32u5x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for stm32u5x family
   4 # stm32u5x devices support both JTAG and SWD transports.
   5
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10         set _CHIPNAME $CHIPNAME
  11 } else {
  12         set _CHIPNAME stm32u5x
  13 }
  14
  15 source [find target/stm32x5x_common.cfg]
  16
  17 proc stm32u5x_clock_config {} {
  18         set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
  19         # MCU clock is at MSI 4MHz after reset, set MCU freq at 160 MHz with PLL
  20
  21         # Enable voltage range 1 for frequency above 100 Mhz
  22         # RCC_AHB3ENR = PWREN
  23         mww [expr {0x46020C94 + $offset}] 0x00000004
  24         # delay for register clock enable (read back reg)
  25         mrw [expr {0x46020C94 + $offset}]
  26         # PWR_VOSR : VOS Range 1
  27         mmw [expr {0x4602080C + $offset}] 0x00030000 0
  28         # while !(PWR_VOSR & VOSRDY)
  29         while {!([mrw [expr {0x4602080C + $offset}]] & 0x00008000)} {}
  30         # FLASH_ACR : 4 WS for 160 MHz HCLK
  31         mww [expr {0x40022000 + $offset}] 0x00000004
  32         # RCC_PLL1CFGR => PLL1MBOOST=0, PLL1M=0=/1, PLL1FRACEN=0, PLL1SRC=MSI 4MHz
  33         #                 PLL1REN=1, PLL1RGE => VCOInputRange=PLLInputRange_4_8
  34         mww [expr {0x46020C28 + $offset}] 0x00040009
  35         # Enable EPOD Booster
  36         mmw [expr {0x4602080C + $offset}] 0x00040000 0
  37         # while !(PWR_VOSR & BOOSTRDY)
  38         while {!([mrw [expr {0x4602080C + $offset}]] & 0x00004000)} {}
  39         # RCC_PLL1DIVR => PLL1P=PLL1Q=PLL1R=000001=/2, PLL1N=0x4F=80
  40         # fVCO = 4 x 80 /1 = 320
  41         # SYSCLOCK = fVCO/PLL1R = 320/2 = 160 MHz
  42         mww [expr {0x46020C34 + $offset}] 0x0101024F
  43         # RCC_CR |= PLL1ON
  44         mmw [expr {0x46020C00 + $offset}] 0x01000000 0
  45         # while !(RCC_CR & PLL1RDY)
  46         while {!([mrw [expr {0x46020C00 + $offset}]] & 0x02000000)} {}
  47         # RCC_CFGR1 |= SW_PLL
  48         mmw [expr {0x46020C1C + $offset}] 0x00000003 0
  49         # while ((RCC_CFGR1 & SWS) != PLL)
  50         while {([mrw [expr {0x46020C1C + $offset}]] & 0x0C) != 0x0C} {}
  51 }
  52
  53 $_TARGETNAME configure -event reset-init {
  54         stm32u5x_clock_config
  55         # Boost JTAG frequency
  56         adapter speed 4000
  57 }