tcl/target/stm32wlx.cfg

   1 # script for stm32wlx family
   2
   3 #
   4 # stm32wl devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10         set _CHIPNAME $CHIPNAME
  11 } else {
  12         set _CHIPNAME stm32wlx
  13 }
  14
  15 if { [info exists DUAL_CORE] } {
  16         set $_CHIPNAME.DUAL_CORE $DUAL_CORE
  17         unset DUAL_CORE
  18 } else {
  19         set $_CHIPNAME.DUAL_CORE 0
  20 }
  21
  22 if { [info exists WKUP_CM0P] } {
  23         set $_CHIPNAME.WKUP_CM0P $WKUP_CM0P
  24         unset WKUP_CM0P
  25 } else {
  26         set $_CHIPNAME.WKUP_CM0P 0
  27 }
  28
  29 # Issue a warning when hla is used, and fallback to single core configuration
  30 if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
  31         echo "Warning : hla does not support multicore debugging"
  32         set $_CHIPNAME.DUAL_CORE 0
  33         set $_CHIPNAME.WKUP_CM0P 0
  34 }
  35
  36 # setup the Work-area start address and size
  37 # Work-area is a space in RAM used for flash programming
  38
  39 # Memory map for known devices:
  40 # STM32WL   x5JC   x5JB   x5J8
  41 #   FLASH   256    128    64
  42 #   SRAM1   32     16     0
  43 #   SRAM2   32     32     20
  44
  45 # By default use 8kB
  46 if { [info exists WORKAREASIZE] } {
  47         set _WORKAREASIZE $WORKAREASIZE
  48 } else {
  49         set _WORKAREASIZE 0x2000
  50 }
  51
  52 # Use SRAM2 as work area (some devices do not have SRAM1):
  53 set WORKAREASTART_CM4   0x20008000
  54 set WORKAREASTART_CM0P  [expr {$WORKAREASTART_CM4 + $_WORKAREASIZE}]
  55
  56 #jtag scan chain
  57 if { [info exists CPUTAPID] } {
  58         set _CPUTAPID $CPUTAPID
  59 } else {
  60         if { [using_jtag] } {
  61                 set _CPUTAPID 0x6ba00477
  62         } else {
  63                 # SWD IDCODE (single drop, arm)
  64                 set _CPUTAPID 0x6ba02477
  65         }
  66 }
  67
  68 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  69 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  70
  71 if {[using_jtag]} {
  72         jtag newtap $_CHIPNAME bs -irlen 5
  73 }
  74
  75 target create $_CHIPNAME.cpu0 cortex_m -endian little -dap $_CHIPNAME.dap
  76
  77 $_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM4 -work-area-size $_WORKAREASIZE -work-area-backup 0
  78
  79 flash bank $_CHIPNAME.flash.cpu0 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu0
  80 flash bank $_CHIPNAME.otp.cpu0   stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu0
  81
  82 if {![using_hla]} {
  83         # if srst is not fitted use SYSRESETREQ to
  84         # perform a soft reset
  85         $_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
  86 }
  87
  88 $_CHIPNAME.cpu0 configure -event reset-init {
  89         # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
  90         # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
  91         # 2 WS compliant with VOS=Range1 and 24 MHz.
  92         mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTEN | 2(Latency)
  93         mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz
  94         # Boost JTAG frequency
  95         adapter speed 4000
  96 }
  97
  98 $_CHIPNAME.cpu0 configure -event reset-start {
  99         # Reset clock is MSI (4 MHz)
 100         adapter speed 500
 101 }
 102
 103 $_CHIPNAME.cpu0 configure -event examine-end {
 104         # Enable debug during low power modes (uses more power)
 105         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
 106         mmw 0xE0042004 0x00000007 0
 107
 108         # Stop watchdog counters during halt
 109         # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
 110         mmw 0xE004203C 0x00001800 0
 111
 112         set _CHIPNAME [stm32wlx_get_chipname]
 113         global $_CHIPNAME.WKUP_CM0P
 114
 115         if {[set $_CHIPNAME.WKUP_CM0P]} {
 116                 stm32wlx_wkup_cm0p
 117         }
 118 }
 119
 120 $_CHIPNAME.cpu0 configure -event trace-config {
 121         # nothing to do
 122 }
 123
 124 if {[set $_CHIPNAME.DUAL_CORE]} {
 125         target create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
 126
 127         $_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM0P -work-area-size $_WORKAREASIZE -work-area-backup 0
 128
 129         flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1
 130         flash bank $_CHIPNAME.otp.cpu1   stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu1
 131
 132         if {![using_hla]} {
 133                 # if srst is not fitted use SYSRESETREQ to
 134                 # perform a soft reset
 135                 $_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
 136         }
 137
 138         proc stm32wlx_wkup_cm0p {} {
 139                 set _CHIPNAME [stm32wlx_get_chipname]
 140
 141                 # enable CPU2 boot after reset and after wakeup from Stop or Standby mode
 142                 # PWR_CR4 |= C2BOOT
 143                 stm32wlx_mmw $_CHIPNAME.cpu0 0x5800040C 0x00008000 0
 144         }
 145 }
 146
 147 # get _CHIPNAME from current target
 148 proc stm32wlx_get_chipname {} {
 149         set t [target current]
 150         set sep [string last "." $t]
 151         if {$sep == -1} {
 152                 return $t
 153         }
 154         return [string range $t 0 [expr {$sep - 1}]]
 155 }
 156
 157 # like mrw, but with target selection
 158 proc stm32wlx_mrw {used_target reg} {
 159         set value ""
 160         $used_target mem2array value 32 $reg 1
 161         return $value(0)
 162 }
 163
 164 # like mmw, but with target selection
 165 proc stm32wlx_mmw {used_target reg setbits clearbits} {
 166         set old [stm32wlx_mrw $used_target $reg]
 167         set new [expr {($old & ~$clearbits) | $setbits}]
 168         $used_target mww $reg $new
 169 }
 170
 171 # Make sure that cpu0 is selected
 172 targets $_CHIPNAME.cpu0
 173
 174 # Common knowledges tells JTAG speed should be <= F_CPU/6.
 175 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
 176 # the safe side.
 177 #
 178 # Note that there is a pretty wide band where things are
 179 # more or less stable, see http://openocd.zylin.com/#/c/3366/
 180 adapter speed 500
 181
 182 adapter srst delay 100
 183 if {[using_jtag]} {
 184         jtag_ntrst_delay 100
 185 }
 186
 187 reset_config srst_nogate