tcl/target/stm32x5x_common.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # common script for stm32l5x and stm32u5x families
   4
   5 # Work-area is a space in RAM used for flash programming
   6 # By default use 64kB
   7 if { [info exists WORKAREASIZE] } {
   8         set _WORKAREASIZE $WORKAREASIZE
   9 } else {
  10         set _WORKAREASIZE 0x10000
  11 }
  12
  13 #jtag scan chain
  14 if { [info exists CPUTAPID] } {
  15         set _CPUTAPID $CPUTAPID
  16 } else {
  17         if { [using_jtag] } {
  18                 # STM32L5x: RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
  19                 # STM32U5x: RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
  20                 # Corresponds to Cortex®-M33 JTAG debug port ID code
  21                 set _CPUTAPID 0x0ba04477
  22         } {
  23                 # SWD IDCODE (single drop, arm)
  24                 set _CPUTAPID 0x0be12477
  25         }
  26 }
  27
  28 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  29 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  30
  31 if {[using_jtag]} {
  32         jtag newtap $_CHIPNAME bs -irlen 5
  33 }
  34
  35 set _TARGETNAME $_CHIPNAME.cpu
  36 target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
  37
  38 # use non-secure RAM by default
  39 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  40
  41 # create sec/ns flash and otp memories (sizes will be probed)
  42 flash bank $_CHIPNAME.flash_ns      stm32l4x 0x08000000 0 0 0 $_TARGETNAME
  43 flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
  44 flash bank $_CHIPNAME.otp           stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
  45
  46 # Common knowledge tells JTAG speed should be <= F_CPU/6.
  47 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
  48 # the safe side.
  49 #
  50 # Note that there is a pretty wide band where things are
  51 # more or less stable, see http://review.openocd.org/3366
  52 adapter speed 500
  53
  54 adapter srst delay 100
  55 if {[using_jtag]} {
  56         jtag_ntrst_delay 100
  57 }
  58
  59 reset_config srst_nogate
  60
  61 if {![using_hla]} {
  62         # if srst is not fitted use SYSRESETREQ to
  63         # perform a soft reset
  64         cortex_m reset_config sysresetreq
  65 }
  66
  67 proc stm32x5x_is_secure {} {
  68         # read Debug Security Control and Status Register (DSCSR) and check CDS (bit 16)
  69         set DSCSR [mrw 0xE000EE08]
  70         return [expr {($DSCSR & (1 << 16)) != 0}]
  71 }
  72
  73 proc stm32x5x_ahb_ap_non_secure_access {} {
  74         # SPROT=1=Non Secure access, Priv=1
  75         [[target current] cget -dap] apcsw 0x4B000000 0x4F000000
  76 }
  77
  78 proc stm32x5x_ahb_ap_secure_access {} {
  79         # SPROT=0=Secure access, Priv=1
  80         [[target current] cget -dap] apcsw 0x0B000000 0x4F000000
  81 }
  82
  83 $_TARGETNAME configure -event reset-start {
  84         # Reset clock is MSI (4 MHz)
  85         adapter speed 480
  86 }
  87
  88 $_TARGETNAME configure -event examine-end {
  89         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
  90         mmw 0xE0044004 0x00000006 0
  91
  92         # Stop watchdog counters during halt
  93         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  94         mmw 0xE0044008 0x00001800 0
  95 }
  96
  97 $_TARGETNAME configure -event halted {
  98         set secure [stm32x5x_is_secure]
  99
 100         if {$secure} {
 101                 set secure_str "Secure"
 102                 stm32x5x_ahb_ap_secure_access
 103         } else {
 104                 set secure_str "Non-Secure"
 105                 stm32x5x_ahb_ap_non_secure_access
 106         }
 107
 108         # print the secure state only when it changes
 109         set _TARGETNAME [target current]
 110         global $_TARGETNAME.secure
 111
 112         if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
 113                 echo "CPU in $secure_str state"
 114                 # update saved security state
 115                 set $_TARGETNAME.secure $secure
 116         }
 117 }
 118
 119 $_TARGETNAME configure -event gdb-flash-erase-start {
 120         set use_secure_workarea 0
 121         # check if FLASH_OPTR.TZEN is enabled
 122         set FLASH_OPTR [mrw 0x40022040]
 123         if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
 124                 echo "TZEN option bit disabled"
 125                 stm32x5x_ahb_ap_non_secure_access
 126         } else {
 127                 stm32x5x_ahb_ap_secure_access
 128                 echo "TZEN option bit enabled"
 129
 130                 # check if FLASH_OPTR.RDP is not Level 0.5
 131                 if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
 132                         set use_secure_workarea 1
 133                 }
 134         }
 135
 136         set _TARGETNAME [target current]
 137         set workarea_addr [$_TARGETNAME cget -work-area-phys]
 138         echo "workarea_addr $workarea_addr"
 139
 140         if {$use_secure_workarea} {
 141                 set workarea_addr [expr {$workarea_addr | 0x10000000}]
 142         } else {
 143                 set workarea_addr [expr {$workarea_addr & ~0x10000000}]
 144         }
 145
 146         $_TARGETNAME configure -work-area-phys $workarea_addr
 147 }
 148
 149 tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
 150
 151 lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
 152 proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
 153         targets $_targetname
 154
 155         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 156         # change this value accordingly to configure trace pins
 157         # assignment
 158         mmw 0xE0044004 0x00000020 0
 159 }
 160
 161 $_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"