tcl/target/ti_dm6446.cfg

   1 #
   2 # Texas Instruments DaVinci family: TMS320DM6446
   3 #
   4 if { [info exists CHIPNAME] } {
   5    set _CHIPNAME $CHIPNAME
   6 } else {
   7    set _CHIPNAME dm6446
   8 }
   9
  10 # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
  11 # after JTAG reset until ICEpick is used to route them in.
  12 set EMU01 "-disable"
  13
  14 # With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
  15 # needing any ICEpick interaction.
  16 #set EMU01 "-enable"
  17
  18 source [find target/icepick.cfg]
  19
  20 # Subsidiary TAP: unknown ... must enable via ICEpick
  21 jtag newtap $_CHIPNAME unknown -irlen 8 -disable
  22 jtag configure $_CHIPNAME.unknown -event tap-enable \
  23         "icepick_c_tapenable $_CHIPNAME.jrc 3"
  24
  25 # Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
  26 jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
  27 jtag configure $_CHIPNAME.dsp -event tap-enable \
  28         "icepick_c_tapenable $_CHIPNAME.jrc 2"
  29
  30 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
  31 if { [info exists ETB_TAPID] } {
  32    set _ETB_TAPID $ETB_TAPID
  33 } else {
  34    set _ETB_TAPID 0x2b900f0f
  35 }
  36 jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
  37 jtag configure $_CHIPNAME.etb -event tap-enable \
  38         "icepick_c_tapenable $_CHIPNAME.jrc 1"
  39
  40 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
  41 if { [info exists CPU_TAPID] } {
  42    set _CPU_TAPID $CPU_TAPID
  43 } else {
  44    set _CPU_TAPID 0x07926001
  45 }
  46 jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
  47 jtag configure $_CHIPNAME.arm -event tap-enable \
  48         "icepick_c_tapenable $_CHIPNAME.jrc 0"
  49
  50 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
  51 if { [info exists JRC_TAPID] } {
  52    set _JRC_TAPID $JRC_TAPID
  53 } else {
  54    set _JRC_TAPID 0x0b70002f
  55 }
  56 jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
  57
  58 jtag configure $_CHIPNAME.jrc -event setup \
  59         "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
  60
  61 ################
  62 # GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
  63 # and the ETB memory (4K) are other options, while trace is unused.
  64 # Little-endian; use the OpenOCD default.
  65 set _TARGETNAME $_CHIPNAME.arm
  66
  67 target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
  68 $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
  69
  70 # be absolutely certain the JTAG clock will work with the worst-case
  71 # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
  72 # on the PLL and starts using it.  OK to speed up after clock setup.
  73 adapter speed 1500
  74 $_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
  75
  76 arm7_9 fast_memory_access enable
  77 arm7_9 dcc_downloads enable
  78
  79 # trace setup
  80 etm config $_TARGETNAME 16 normal full etb
  81 etb config $_TARGETNAME $_CHIPNAME.etb