tcl/target/xilinx_zynqmp.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #
   4 # target configuration for
   5 # Xilinx ZynqMP (UltraScale+ / A53)
   6 #
   7 if { [info exists CHIPNAME] } {
   8     set _CHIPNAME $CHIPNAME
   9 } else {
  10     set _CHIPNAME uscale
  11 }
  12
  13 #
  14 # DAP tap (Quard core A53)
  15 #
  16 if { [info exists DAP_TAPID] } {
  17     set _DAP_TAPID $DAP_TAPID
  18 } else {
  19     set _DAP_TAPID 0x5ba00477
  20 }
  21
  22 jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID
  23 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
  24
  25 #
  26 # PS tap (UltraScale+)
  27 #
  28 if { [info exists PS_TAPID] } {
  29     set _PS_TAPID $PS_TAPID
  30     jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID
  31 } else {
  32     # FPGA Programmable logic. Values take from Table 39-1 in UG1085:
  33     jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -ignore-version \
  34         -expected-id 0x04711093 \
  35         -expected-id 0x04710093 \
  36         -expected-id 0x04721093 \
  37         -expected-id 0x04720093 \
  38         -expected-id 0x04739093 \
  39         -expected-id 0x04730093 \
  40         -expected-id 0x04738093 \
  41         -expected-id 0x04740093 \
  42         -expected-id 0x04750093 \
  43         -expected-id 0x04759093 \
  44         -expected-id 0x04758093
  45 }
  46
  47 set jtag_configured 0
  48
  49 jtag configure $_CHIPNAME.ps -event setup {
  50     global _CHIPNAME
  51     global jtag_configured
  52
  53     if { $jtag_configured == 0 } {
  54         # add the DAP tap to the chain
  55         # See https://forums.xilinx.com/t5/UltraScale-Architecture/JTAG-Chain-Configuration-for-Zynq-UltraScale-MPSoC/td-p/758924
  56         irscan $_CHIPNAME.ps 0x824
  57         drscan $_CHIPNAME.ps 32 0x00000003
  58         runtest 100
  59
  60         # setup event will be re-entered through jtag arp_init
  61         # break the recursion
  62         set jtag_configured 1
  63         # re-initialized the jtag chain
  64         jtag arp_init
  65     }
  66 }
  67
  68 set _TARGETNAME $_CHIPNAME.a53
  69 set _CTINAME $_CHIPNAME.cti
  70 set _smp_command ""
  71
  72 set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
  73 set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
  74 set _cores 4
  75
  76 for { set _core 0 } { $_core < $_cores } { incr _core } {
  77
  78     cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
  79         -baseaddr [lindex $CTIBASE $_core]
  80
  81     set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
  82         -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
  83
  84     if { $_core != 0 } {
  85         # non-boot core examination may fail
  86         set _command "$_command -defer-examine"
  87         set _smp_command "$_smp_command $_TARGETNAME.$_core"
  88     } else {
  89         # uncomment when "hawt" rtos is merged
  90         #set _command "$_command -rtos hawt"
  91         set _smp_command "target smp $_TARGETNAME.$_core"
  92     }
  93
  94     eval $_command
  95 }
  96
  97 target create uscale.axi mem_ap -dap uscale.dap -ap-num 0
  98
  99 eval $_smp_command
 100 targets $_TARGETNAME.0
 101
 102 proc core_up { args } {
 103     global _TARGETNAME
 104     foreach core $args {
 105         $_TARGETNAME.$core arp_examine
 106     }
 107 }