tcl/target/xilinx_zynqmp.cfg

   1 #
   2 # target configuration for
   3 # Xilinx ZynqMP (UltraScale+ / A53)
   4 #
   5 if { [info exists CHIPNAME] } {
   6     set _CHIPNAME $CHIPNAME
   7 } else {
   8     set _CHIPNAME uscale
   9 }
  10
  11 #
  12 # DAP tap (Quard core A53)
  13 #
  14 if { [info exists DAP_TAPID] } {
  15     set _DAP_TAPID $DAP_TAPID
  16 } else {
  17     set _DAP_TAPID 0x5ba00477
  18 }
  19
  20 jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID
  21 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
  22
  23 #
  24 # PS tap (UltraScale+)
  25 #
  26 if { [info exists PS_TAPID] } {
  27     set _PS_TAPID $PS_TAPID
  28     jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID
  29 } else {
  30     # FPGA Programmable logic. Values take from Table 39-1 in UG1085:
  31     jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -ignore-version \
  32         -expected-id 0x04711093 \
  33         -expected-id 0x04710093 \
  34         -expected-id 0x04721093 \
  35         -expected-id 0x04720093 \
  36         -expected-id 0x04739093 \
  37         -expected-id 0x04730093 \
  38         -expected-id 0x04738093 \
  39         -expected-id 0x04740093 \
  40         -expected-id 0x04750093 \
  41         -expected-id 0x04759093 \
  42         -expected-id 0x04758093
  43 }
  44
  45 set jtag_configured 0
  46
  47 jtag configure $_CHIPNAME.ps -event setup {
  48     global _CHIPNAME
  49     global jtag_configured
  50
  51     if { $jtag_configured == 0 } {
  52         # add the DAP tap to the chain
  53         # See https://forums.xilinx.com/t5/UltraScale-Architecture/JTAG-Chain-Configuration-for-Zynq-UltraScale-MPSoC/td-p/758924
  54         irscan $_CHIPNAME.ps 0x824
  55         drscan $_CHIPNAME.ps 32 0x00000003
  56         runtest 100
  57
  58         # setup event will be re-entered through jtag arp_init
  59         # break the recursion
  60         set jtag_configured 1
  61         # re-initialized the jtag chain
  62         jtag arp_init
  63     }
  64 }
  65
  66 set _TARGETNAME $_CHIPNAME.a53
  67 set _CTINAME $_CHIPNAME.cti
  68 set _smp_command ""
  69
  70 set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
  71 set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
  72 set _cores 4
  73
  74 for { set _core 0 } { $_core < $_cores } { incr _core } {
  75
  76     cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
  77         -baseaddr [lindex $CTIBASE $_core]
  78
  79     set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
  80         -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
  81
  82     if { $_core != 0 } {
  83         # non-boot core examination may fail
  84         set _command "$_command -defer-examine"
  85         set _smp_command "$_smp_command $_TARGETNAME.$_core"
  86     } else {
  87         # uncomment when "hawt" rtos is merged
  88         #set _command "$_command -rtos hawt"
  89         set _smp_command "target smp $_TARGETNAME.$_core"
  90     }
  91
  92     eval $_command
  93 }
  94
  95 target create uscale.axi mem_ap -dap uscale.dap -ap-num 0
  96
  97 eval $_smp_command
  98 targets $_TARGETNAME.0
  99
 100 proc core_up { args } {
 101     global _TARGETNAME
 102     foreach { core } [set args] {
 103         $_TARGETNAME.$core arp_examine
 104     }
 105 }