tcl/target/zynq_7000.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #
   4 # Xilinx Zynq-7000 All Programmable SoC
   5 #
   6 # http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm
   7 #
   8
   9 set _CHIPNAME zynq
  10 set _TARGETNAME $_CHIPNAME.cpu
  11
  12 jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \
  13     -expected-id 0x23727093 \
  14     -expected-id 0x13722093 \
  15     -expected-id 0x03727093 \
  16     -expected-id 0x03736093
  17
  18 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
  19
  20 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  21
  22 target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap \
  23     -coreid 0 -dbgbase 0x80090000
  24 target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
  25     -coreid 1 -dbgbase 0x80092000
  26 target smp ${_TARGETNAME}0 ${_TARGETNAME}1
  27
  28 adapter speed 1000
  29
  30 ${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
  31 ${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
  32
  33 pld device virtex2 zynq_pl.bs 1
  34
  35 set XC7_JSHUTDOWN 0x0d
  36 set XC7_JPROGRAM 0x0b
  37 set XC7_JSTART 0x0c
  38 set XC7_BYPASS 0x3f
  39
  40 proc zynqpl_program {tap} {
  41         global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
  42         irscan $tap $XC7_JSHUTDOWN
  43         irscan $tap $XC7_JPROGRAM
  44         runtest 60000
  45         #JSTART prevents this from working...
  46         #irscan $tap $XC7_JSTART
  47         runtest 2000
  48         irscan $tap $XC7_BYPASS
  49         runtest 2000
  50 }