1 /****************************************************************************
2 * Copyright (c) 2006 by Michael Fischer. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of its contributors may
14 * be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
20 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
24 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
27 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 ****************************************************************************
34 * 09.04.06 mifi First Version
35 ****************************************************************************/
38 * Some defines for the program status registers
40 ARM_MODE_USER = 0x10 /* Normal User Mode */
41 ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
42 ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
43 ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
44 ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
45 ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
46 ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */
49 I_BIT = 0x80 /* disable IRQ when I bit is set */
50 F_BIT = 0x40 /* disable IRQ when I bit is set */
53 .section .vectors,"ax"
56 /****************************************************************************/
57 /* Vector table and reset entry */
58 /****************************************************************************/
60 ldr pc, ResetAddr /* Reset */
61 ldr pc, UndefAddr /* Undefined instruction */
62 ldr pc, SWIAddr /* Software interrupt */
63 ldr pc, PAbortAddr /* Prefetch abort */
64 ldr pc, DAbortAddr /* Data abort */
65 ldr pc, ReservedAddr /* Reserved */
66 ldr pc, IRQAddr /* IRQ interrupt */
67 ldr pc, FIQAddr /* FIQ interrupt */
70 ResetAddr: .word ResetHandler
71 UndefAddr: .word UndefHandler
72 SWIAddr: .word SWIHandler
73 PAbortAddr: .word PAbortHandler
74 DAbortAddr: .word DAbortHandler
76 IRQAddr: .word IRQHandler
77 FIQAddr: .word FIQHandler
88 /****************************************************************************/
90 /****************************************************************************/
93 * Setup a stack for each mode
95 msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
96 ldr sp, =__stack_und_end
98 msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
99 ldr sp, =__stack_abt_end
101 msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
102 ldr sp, =__stack_fiq_end
104 msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
105 ldr sp, =__stack_irq_end
107 msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
108 ldr sp, =__stack_svc_end
127 bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */
130 mov r0, #0 /* No arguments */
131 mov r1, #0 /* No arguments */
134 bx r2 /* And jump... */
143 /****************************************************************************/
144 /* Default interrupt handler */
145 /****************************************************************************/
166 .weak UndefHandler, PAbortHandler, DAbortHandler
167 .weak IRQHandler, FIQHandler