testing/examples/STR912Test/src/startup.s

   1 /***********************************************************************************
   2 *       Copyright 2005 Anglia Design
   3 *       This demo code and associated components are provided as is and has no warranty,
   4 *       implied or otherwise.  You are free to use/modify any of the provided
   5 *       code at your own risk in your applications with the expressed limitation
   6 *       of liability (see below)
   7 *
   8 *       LIMITATION OF LIABILITY:   ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
   9 *       LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
  10 *       INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
  11 *       THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
  12 *
  13 *       Author  : Spencer Oliver
  14 *       Web             : www.anglia-designs.com
  15 *
  16 *     mifi, 22.01.2008, small changes by the init of the C++ eabi constructors.
  17 *                       Here I have replaced the eabi init by the normal init.
  18 *                       Thanks to Spen for the startup code.
  19 ***********************************************************************************/
  20
  21 /**** Startup Code (executed after Reset) ****/
  22
  23 /* Frequency values kHz */
  24 /* set to suit target hardware */
  25
  26         .equ    FOSC,                   25000
  27
  28 /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
  29
  30         .equ    Mode_USR,               0x10
  31         .equ    Mode_FIQ,               0x11
  32         .equ    Mode_IRQ,               0x12
  33         .equ    Mode_SVC,               0x13
  34         .equ    Mode_ABT,               0x17
  35         .equ    Mode_UND,               0x1B
  36         .equ    Mode_SYS,               0x1F                    /* available on ARM Arch 4 and later */
  37
  38         .equ    I_Bit,                  0x80                    /* when I bit is set, IRQ is disabled */
  39         .equ    F_Bit,                  0x40                    /* when F bit is set, FIQ is disabled */
  40
  41         .equ    SRAM32,                 0x00
  42         .equ    SRAM64,                 0x08
  43         .equ    SRAM96,                 0x10
  44
  45 /* --- System memory locations */
  46
  47         .equ    SCRO_AHB_UMB,           0x5C002034              /* System configuration register 0 (unbuffered) */
  48
  49         .equ    FMI_BASE_UMB,           0x54000000              /* Flash FMI base address (unbuffered) */
  50         .equ    BBSR_off_addr,          0x00
  51         .equ    NBBSR_off_addr,         0x04
  52         .equ    BBADR_off_addr,         0x0C
  53         .equ    NBBADR_off_addr,        0x10
  54         .equ    CR_off_addr,            0x18
  55
  56 .ifndef LIBUFF
  57         .equ    LIBUFF, 0
  58 .endif
  59
  60 /* Startup Code must be linked first at Address at which it expects to run. */
  61
  62         .text
  63         .arm
  64         .section .init, "ax"
  65
  66         .global _start
  67         .global _Main_Crystal
  68
  69 /* After remap this will be our reset handler */
  70
  71 _start:
  72                 LDR     pc, =NextInst
  73 NextInst:
  74
  75                 NOP             /* Wait for OSC stabilization */
  76                 NOP
  77                 NOP
  78                 NOP
  79                 NOP
  80                 NOP
  81                 NOP
  82                 NOP
  83                 NOP
  84
  85 /* Enable buffered mode */
  86
  87 .if LIBUFF
  88                 MRC             p15, 0, r0, c1, c0, 0           /* Read CP15 register 1 into r0 */
  89                 ORR             r0, r0, #0x8                            /* Enable Write Buffer on AHB */
  90                 MCR             p15, 0, r0, c1, c0, 0           /* Write CP15 register 1 */
  91 .endif
  92
  93 /* Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, */
  94 /* when the bank 0 is the boot bank, then enable the Bank 1. */
  95
  96                 LDR             r0, =FMI_BASE_UMB
  97                 LDR             r1, =0x4                                        /* configure 512KB Boot bank 0 */
  98                 STR             r1, [r0, #BBSR_off_addr]
  99
 100                 LDR             r1, =0x2                                        /* configure 32KB Non Boot bank 1 */
 101                 STR             r1, [r0, #NBBSR_off_addr]
 102
 103                 LDR             r1, =(0x00000000 >> 2)          /* Boot Bank Base Address */
 104                 STR             r1, [r0, #BBADR_off_addr]
 105
 106                 LDR             r1, =(0x00080000 >> 2)          /* Non Boot Bank Base Address */
 107                 STR             r1, [r0, #NBBADR_off_addr]
 108
 109                 LDR             r1, =0x18                                       /* Flash Banks 0 1 enabled */
 110                 STR             r1, [r0, #CR_off_addr]
 111
 112 /* Enable 96K RAM */
 113
 114                 LDR             r0, =SCRO_AHB_UMB
 115 #               LDR             r1, =0x0196                             /* prefetch disabled, default enabled */
 116                 LDR             r1, =0x0187|SRAM96
 117                 STR             r1, [r0]
 118
 119 /* Set bits 17-18 (Instruction/Data TCM order) of the */
 120 /* Core Configuration Control Register */
 121
 122                 MOV             r0, #0x60000
 123                 MCR             p15, 0x1, r0, c15, c1, 0
 124
 125 /* Setup Stack for each mode */
 126
 127 /* Enter Abort Mode and set its Stack Pointer */
 128
 129                 MSR             cpsr_c, #Mode_ABT|I_Bit|F_Bit
 130                 LDR             sp, =__stack_abt_end__
 131
 132 /* Enter Undefined Instruction Mode and set its Stack Pointer */
 133
 134                 MSR             cpsr_c, #Mode_UND|I_Bit|F_Bit
 135                 LDR             sp, =__stack_und_end__
 136
 137 /* Enter Supervisor Mode and set its Stack Pointer */
 138
 139                 MSR             cpsr_c, #Mode_SVC|I_Bit|F_Bit
 140                 LDR             sp, =__stack_svc_end__
 141
 142 /* Enter FIQ Mode and set its Stack Pointer */
 143
 144                 MSR             cpsr_c, #Mode_FIQ|I_Bit|F_Bit
 145                 LDR             sp, =__stack_fiq_end__
 146
 147 /* Enter IRQ Mode and set its Stack Pointer */
 148
 149                 MSR             cpsr_c, #Mode_IRQ|I_Bit|F_Bit
 150                 LDR             sp, =__stack_irq_end__
 151
 152 /* Enter System/User Mode and set its Stack Pointer */
 153
 154                 MSR             cpsr_c, #Mode_SYS
 155                 LDR             sp, =__stack_end__
 156
 157 /* Setup a default Stack Limit (when compiled with "-mapcs-stack-check") */
 158
 159                 LDR             sl, =__bss_end__
 160
 161 /* Relocate .data section (Copy from ROM to RAM) */
 162
 163                 LDR             r1, =_etext
 164                 LDR             r2, =__data_start
 165                 LDR             r3, =_edata
 166 LoopRel:
 167                 CMP             r2, r3
 168                 LDRLO   r0, [r1], #4
 169                 STRLO   r0, [r2], #4
 170                 BLO             LoopRel
 171
 172 /* Clear .bss section (Zero init) */
 173
 174                 MOV             r0, #0
 175                 LDR             r1, =__bss_start__
 176                 LDR             r2, =__bss_end__
 177 LoopZI:
 178                 CMP             r1, r2
 179                 STRLO   r0, [r1], #4
 180                 BLO             LoopZI
 181
 182 /* Call C++ constructors */
 183
 184                 LDR             r0, =__ctors_start__
 185                 LDR             r1, =__ctors_end__
 186 ctor_loop:
 187                 CMP             r0, r1
 188                 BEQ             ctor_end
 189                 LDR             r2, [r0], #4
 190                 STMFD   sp!, {r0-r1}
 191                 BLX             r2
 192                 LDMFD           sp!, {r0-r1}
 193                 B               ctor_loop
 194 ctor_end:
 195
 196 /* Need to set up standard file handles */
 197 /* Only used under simulator, normally overide syscall.c */
 198
 199 #               BL              initialise_monitor_handles
 200
 201 /* if we use debug version of str9lib this will call the init function */
 202
 203                 BL              libdebug
 204 libdebug:
 205
 206 /* Enter the C code, use B instruction so as to never return */
 207 /* use BL main if you want to use c++ destructors below */
 208
 209                 B               main
 210
 211 /* Return from main, loop forever. */
 212
 213 #exit_loop:
 214 #               B               exit_loop
 215
 216 /* Fosc values, used by libstr9 */
 217
 218 _Main_Crystal:  .long   FOSC
 219
 220         .weak libdebug
 221
 222         .end