testing/examples/cortex/cm3-ftest.cfg

   1 #
   2 # For each named Cortex-M3 vector_catch flag VECTOR ...
   3 #               bus_err         state_err
   4 #               chk_err         nocp_err
   5 #               mm_err          reset
   6 #
   7 # BUT NYET hard_err, int_err (their test cases don't yet work) ...
   8 #
   9 # Do the following:
  10 #
  11 #  - Test #1:  verify that OpenOCD ignores exceptions by default
  12 #     + l_VECTOR (loads testcase to RAM)
  13 #     + fault triggers loop-to-self exception "handler"
  14 #     + "halt"
  15 #     + observe fault "handling" -- loop-to-self from load_and_run (below)
  16 #
  17 #  - Test #2:  verify that "vector_catch" makes OpenOCD stops ignoring them
  18 #     + cortex_m3 vector_catch none
  19 #     + cortex_m3 vector_catch VECTOR
  20 #     + l_VECTOR (loads testcase to RAM)
  21 #     + fault triggers vector catch hardware
  22 #     + observe OpenOCD entering debug state with no assistance
  23 #
  24 # NOTE "reset" includes the NVIC, so that test case gets its reset vector
  25 # from the flash, not from the vector table set up here.  Which means that
  26 # for that vector_catch option, the Test #1 (above) "observe" step won't
  27 # use the SRAM address.
  28 #
  29
  30 # we can fully automate test #2
  31 proc vector_test {tag} {
  32         halt
  33         # REVISIT -- annoying, we'd like to scrap vector_catch output
  34         cortex_m3 vector_catch none
  35         cortex_m3 vector_catch $tag
  36         eval "l_$tag"
  37 }
  38
  39 #
  40 # Load and start one vector_catch test case.
  41 #
  42 # name -- tag for the vector_catch flag being tested
  43 # halfwords -- array of instructions (some wide, some narrow)
  44 # n_instr -- how many instructions are in $halfwords
  45 #
  46 proc load_and_run { name halfwords n_instr } {
  47         reset halt
  48
  49         # Load code at beginning of SRAM.
  50         echo "# code to trigger $name vector"
  51         set addr 0x20000000
  52
  53         # ocd_array2mem should be faster, though we'd need to
  54         # compute the resulting $addr ourselves
  55         foreach opcode $halfwords {
  56                 mwh $addr $opcode
  57                 incr addr 2
  58         }
  59
  60         # create default loop-to-self at $addr ... it serves as
  61         # (a) "main loop" on error
  62         # (b) handler for all exceptions that get triggered
  63         mwh $addr 0xe7fe
  64
  65         # disassemble, as sanity check and what's-happening trace
  66         arm disassemble 0x20000000 [expr 1 + $n_instr ]
  67
  68         # Assume that block of code is at most 16 halfwords long.
  69         # Create a basic table of loop-to-self exception handlers.
  70         mww 0x20000020 $addr 16
  71         # Store its address in VTOR
  72         mww 0xe000ed08 0x20000020
  73         # Use SHCSR to ensure nothing escalates to a HardFault
  74         mww 0xe000ed24 0x00070000
  75
  76         # now start, trigering the $name vector catch logic
  77         resume 0x20000000
  78 }
  79
  80 #proc l_hard_err {} {
  81 #       IMPLEMENT ME
  82 #       FORCED -- escalate something to HardFault
  83 #}
  84
  85 #proc l_int_err {} {
  86 #       IMPLEMENT ME
  87 #       STKERR -- exception stack BusFault
  88 #}
  89
  90 # BusFault, escalates to HardFault
  91 proc l_bus_err {} {
  92         # PRECISERR -- assume less than 512 MBytes of SRAM
  93         load_and_run bus_err {
  94                 0xf06f 0x4040
  95                 0x7800
  96         } 2
  97 }
  98
  99 # UsageFault, escalates to HardFault
 100 proc l_state_err {} {
 101         # UNDEFINSTR -- issue architecturally undefined instruction
 102         load_and_run state_err {
 103                 0xde00
 104         } 1
 105 }
 106
 107 # UsageFault, escalates to HardFault
 108 proc l_chk_err {} {
 109         # UNALIGNED -- LDM through unaligned pointer
 110         load_and_run chk_err {
 111                 0xf04f 0x0001
 112                 0xe890 0x0006
 113         } 2
 114 }
 115
 116 # UsageFault, escalates to HardFault
 117 proc l_nocp_err {} {
 118         # NOCP -- issue cp14 DCC instruction
 119         load_and_run nocp_err {
 120                 0xee10 0x0e15
 121         } 1
 122 }
 123
 124 # MemManage, escalates to HardFault
 125 proc l_mm_err {} {
 126         # IACCVIOL -- instruction fetch from an XN region
 127         load_and_run mm_err {
 128                 0xf04f 0x4060
 129                 0x4687
 130         } 2
 131 }
 132
 133 proc l_reset {} {
 134         # issue SYSRESETREQ via AIRCR
 135         load_and_run reset {
 136                 0xf04f 0x0104
 137                 0xf2c0 0x51fa
 138                 0xf44f 0x406d
 139                 0xf100 0x000c
 140                 0xf2ce 0x0000
 141                 0x6001
 142         } 6
 143 }