# Config for balloon3 board, cpu JTAG port. http://balloonboard.org/ # The board has separate JTAG ports for cpu and CPLD/FPGA devices # Chaining is done on IO interfaces if desired. source [find target/pxa270.cfg] # The board supports separate reset lines # Override this in the interface config for parallel dongles reset_config trst_and_srst separate # flash bank # 29LV650 64Mbit Flash set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 $_TARGETNAME