################################################################################################# # Author: Benjamin Tietz ;# # based on work from: Wjatscheslaw Stoljarski (Slawa) ;# # Kiwigrid GmbH ;# # Generated for In-Circuit i.MX53 SO-Dimm ;# ################################################################################################# # The In-Circuit ICnova IMX53SODIMM board has a single IMX53 chip source [find target/imx53.cfg] # Helper for common memory read/modify/write procedures source [find mem_helper.tcl] echo "i.MX53 SO-Dimm board lodaded." # Set reset type #reset_config srst_only adapter_khz 3000 $_TARGETNAME configure -event "reset-assert" { echo "Reseting ...." #cortex_a dbginit } $_TARGETNAME configure -event reset-init { sodimm_init } global AIPS1_BASE_ADDR set AIPS1_BASE_ADDR 0x53F00000 global AIPS2_BASE_ADDR set AIPS2_BASE_ADDR 0x63F00000 proc sodimm_init { } { echo "Reset-init..." ; # halt the CPU halt echo "HW version [format %x [mrw 0x48]]" dap apsel 1 DCD ; # ARM errata ID #468414 set tR [arm mrc 15 0 1 0 1] arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit init_l2cc init_aips init_clock dap apsel 0 ; # Force ARM state ; #reg cpsr 0x000001D3 arm core_state arm jtag_rclk 3000 # adapter_khz 3000 } # L2CC Cache setup/invalidation/disable proc init_l2cc { } { ; #/* explicitly disable L2 cache */ ; #mrc 15, 0, r0, c1, c0, 1 set tR [arm mrc 15 0 1 0 1] ; #bic r0, r0, #0x2 ; #mcr 15, 0, r0, c1, c0, 1 arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)] ; #/* reconfigure L2 cache aux control reg */ ; #mov r0, #0xC0 /* tag RAM */ ; #add r0, r0, #0x4 /* data RAM */ ; #orr r0, r0, #(1 << 24) /* disable write allocate delay */ ; #orr r0, r0, #(1 << 23) /* disable write allocate combine */ ; #orr r0, r0, #(1 << 22) /* disable write allocate */ ; #mcr 15, 1, r0, c9, c0, 2 arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<22)] } # AIPS setup - Only setup MPROTx registers. # The PACR default values are good. proc init_aips { } { ; # Set all MPROTx to be non-bufferable, trusted for R/W, ; # not forced to user-mode. global AIPS1_BASE_ADDR global AIPS2_BASE_ADDR set VAL 0x77777777 # dap apsel 1 mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL # dap apsel 0 } proc init_clock { } { global AIPS1_BASE_ADDR global AIPS2_BASE_ADDR set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000] set CLKCTL_CCSR 0x0C set CLKCTL_CBCDR 0x14 set CLKCTL_CBCMR 0x18 set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000] set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000] set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000] set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000] set CLKCTL_CSCMR1 0x1C set CLKCTL_CDHIPR 0x48 set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000] set CLKCTL_CSCDR1 0x24 set CLKCTL_CCDR 0x04 ; # Switch ARM to step clock mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4 return echo "not returned" setup_pll $PLL1_BASE_ADDR 800 setup_pll $PLL3_BASE_ADDR 400 ; # Switch peripheral to PLL3 mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154 mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)] while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } setup_pll $PLL2_BASE_ADDR 400 ; # Switch peripheral to PLL2 mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)] mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154 ; # change uart clk parent to pll2 mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000] ; # make sure change is effective while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } setup_pll $PLL3_BASE_ADDR 216 setup_pll $PLL4_BASE_ADDR 455 ; # Set the platform clock dividers mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124 mww [expr $CCM_BASE_ADDR + 0x10] 0 ; # Switch ARM back to PLL 1. mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0 ; # make uart div=6 mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a] ; # Restore the default values in the Gate registers mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000 ; # for cko - for ARM div by 8 mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0] } proc setup_pll { PLL_ADDR CLK } { set PLL_DP_CTL 0x00 set PLL_DP_CONFIG 0x04 set PLL_DP_OP 0x08 set PLL_DP_HFS_OP 0x1C set PLL_DP_MFD 0x0C set PLL_DP_HFS_MFD 0x20 set PLL_DP_MFN 0x10 set PLL_DP_HFS_MFN 0x24 if {$CLK == 1000} { set DP_OP [expr (10 << 4) + ((1 - 1) << 0)] set DP_MFD [expr (12 - 1)] set DP_MFN 5 } elseif {$CLK == 850} { set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] set DP_MFD [expr (48 - 1)] set DP_MFN 41 } elseif {$CLK == 800} { set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] set DP_MFD [expr (3 - 1)] set DP_MFN 1 } elseif {$CLK == 700} { set DP_OP [expr (7 << 4) + ((1 - 1) << 0)] set DP_MFD [expr (24 - 1)] set DP_MFN 7 } elseif {$CLK == 600} { set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] set DP_MFD [expr (4 - 1)] set DP_MFN 1 } elseif {$CLK == 665} { set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] set DP_MFD [expr (96 - 1)] set DP_MFN 89 } elseif {$CLK == 532} { set DP_OP [expr (5 << 4) + ((1 - 1) << 0)] set DP_MFD [expr (24 - 1)] set DP_MFN 13 } elseif {$CLK == 455} { set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] set DP_MFD [expr (48 - 1)] set DP_MFN 71 } elseif {$CLK == 400} { set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] set DP_MFD [expr (3 - 1)] set DP_MFN 1 } elseif {$CLK == 216} { set DP_OP [expr (6 << 4) + ((3 - 1) << 0)] set DP_MFD [expr (4 - 1)] set DP_MFN 3 } else { error "Error (setup_dll): clock not found!" } mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2 mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 } } proc CPU_2_BE_32 { L } { return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)] } # Device Configuration Data proc DCD { } { # dap apsel 1 #*========================================================================================== ====== # Initialization script for 32 bit DDR3 (CS0+CS1) #*========================================================================================== ====== # Remux D24/D25 to perform Flash-access mww 0x53fa818C 0x00000000 ; #EIM_RW mww 0x53fa8180 0x00000000 ; #EIM_CS0 mww 0x53fa8188 0x00000000 ; #EIM_OE mww 0x53fa817C 0x00000000 ; #A16 mww 0x53fa8178 0x00000000 ; #A17 mww 0x53fa8174 0x00000000 ; #A18 mww 0x53fa8170 0x00000000 ; #A19 mww 0x53fa816C 0x00000000 ; #A20 mww 0x53fa8168 0x00000000 ; #A21 mww 0x53fa819C 0x00000000 ; #DA0 mww 0x53fa81A0 0x00000000 ; #DA1 mww 0x53fa81A4 0x00000000 ; #DA2 mww 0x53fa81A8 0x00000000 ; #DA3 mww 0x53fa81AC 0x00000000 ; #DA4 mww 0x53fa81B0 0x00000000 ; #DA5 mww 0x53fa81B4 0x00000000 ; #DA6 mww 0x53fa81B8 0x00000000 ; #DA7 mww 0x53fa81BC 0x00000000 ; #DA8 mww 0x53fa81C0 0x00000000 ; #DA9 mww 0x53fa81C4 0x00000000 ; #DA10 mww 0x53fa81C8 0x00000000 ; #DA11 mww 0x53fa81CC 0x00000000 ; #DA12 mww 0x53fa81D0 0x00000000 ; #DA13 mww 0x53fa81D4 0x00000000 ; #DA14 mww 0x53fa81D8 0x00000000 ; #DA15 mww 0x53fa8118 0x00000000 ; #D16 mww 0x53fa811C 0x00000000 ; #D17 mww 0x53fa8120 0x00000000 ; #D18 mww 0x53fa8124 0x00000000 ; #D19 mww 0x53fa8128 0x00000000 ; #D20 mww 0x53fa812C 0x00000000 ; #D21 mww 0x53fa8130 0x00000000 ; #D22 mww 0x53fa8134 0x00000000 ; #D23 mww 0x53fa813c 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D24 mww 0x53fa8140 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D25 mww 0x53fa8144 0x00000000 ; #D26 mww 0x53fa8148 0x00000000 ; #D27 mww 0x53fa814C 0x00000000 ; #D28 mww 0x53fa8150 0x00000000 ; #D29 mww 0x53fa8154 0x00000000 ; #D30 mww 0x53fa8158 0x00000000 ; #D31 # DDR3 IOMUX configuration #* Global pad control options */ mww 0x53fa8554 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 mww 0x53fa8558 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 mww 0x53fa8560 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 mww 0x53fa8564 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 mww 0x53fa8568 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 mww 0x53fa8570 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - boazp: weaker sdclk EVK DDR max frequency mww 0x53fa8574 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS mww 0x53fa8578 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - boazp: weaker sdclk EVK DDR max frequency mww 0x53fa857c 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 mww 0x53fa8580 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 mww 0x53fa8584 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 mww 0x53fa8588 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS mww 0x53fa8590 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 mww 0x53fa8594 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 mww 0x53fa86f0 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_ADDDS mww 0x53fa86f4 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL mww 0x53fa86fc 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRPKE # mww 0x53fa8714 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX mww 0x53fa8714 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX mww 0x53fa8718 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B0DS mww 0x53fa871c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B1DS mww 0x53fa8720 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_CTLDS mww 0x53fa8724 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=0 XXX mww 0x53fa8728 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B2DS mww 0x53fa872c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B3DS # mww 0x53fa86f4 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL for sDQS[3:0], 1=DDR2, 0=CMOS mode # mww 0x53fa8714 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE for D[31:0], 1=DDR2, 0=CMOS mode # mww 0x53fa86fc 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKE # mww 0x53fa8724 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=00 #* Data bus byte lane pad drive strength control options */ # mww 0x53fa872c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B3DS # mww 0x53fa8554 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 # mww 0x53fa8558 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 # mww 0x53fa8728 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B2DS # mww 0x53fa8560 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 # mww 0x53fa8568 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 # mww 0x53fa871c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B1DS # mww 0x53fa8594 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 # mww 0x53fa8590 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 # mww 0x53fa8718 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B0DS # mww 0x53fa8584 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 # mww 0x53fa857c 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 #* SDCLK pad drive strength control options */ # mww 0x53fa8578 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 # mww 0x53fa8570 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 #* Control and addr bus pad drive strength control options */ # mww 0x53fa8574 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS # mww 0x53fa8588 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS # mww 0x53fa86f0 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_ADDDS for DDR addr bus # mww 0x53fa8720 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_CTLDS for CSD0, CSD1, SDCKE0, SDCKE1, SDWE # mww 0x53fa8564 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 # mww 0x53fa8580 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 # Initialize DDR3 memory - Micron MT41J128M16-187Er #** Keep for now, same setting as CPU3 board **# mww 0x63fd901c 0x00008000 # mww 0x63fd904c 0x01680172 ; #write leveling reg 0 # mww 0x63fd9050 0x0021017f ; #write leveling reg 1 mww 0x63fd9088 0x32383535 ; #read delay lines mww 0x63fd9090 0x40383538 ; #write delay lines # mww 0x63fd90F8 0x00000800 ; #Measure unit mww 0x63fd907c 0x0136014d ; #DQS gating 0 mww 0x63fd9080 0x01510141 ; #DQS gating 1 #* CPU3 Board settingr # Enable bank interleaving, Address mirror on, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0 # mww 0x63fd9018 0x00091740 ; #Misc register: #* Quick Silver board setting # Enable bank interleaving, Address mirror off, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0 mww 0x63fd9018 0x00011740 ; #Misc register # Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit # mww 0x63fd9000 0xc3190000 ; #Main control register # Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit mww 0x63fd9000 0x83190000 ; #Main control register # tRFC=64ck;tXS=68;tXP=3;tXPDLL=10;tFAW=15;CAS=6ck mww 0x63fd900C 0x555952E3 ; #timing configuration Reg 0 # tRCD=6;tRP=6;tRC=21;tRAS=15;tRPA=1;tWR=6;tMRD=4;tCWL=5ck mww 0x63fd9010 0xb68e8b63 ; #timing configuration Reg 1 # tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4 mww 0x63fd9014 0x01ff00db ; #timing configuration Reg 2 mww 0x63fd902c 0x000026d2 ; #command delay (default) mww 0x63fd9030 0x009f0e21 ; #out of reset delays # Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values mww 0x63fd9008 0x12273030 ; #ODT timings # tCKE=3; tCKSRX=5; tCKSRE=5 mww 0x63fd9004 0x0002002d #Power down control #********************************** #DDR device configuration: #********************************** #********************************** # CS0: #********************************** mww 0x63fd901c 0x00008032 ; #write mode reg MR2 with cs0 (see below for settings) # Full array self refresh # Rtt_WR disabled (no ODT at IO CMOS operation) # Manual self refresh # CWS=5 mww 0x63fd901c 0x00008033 ; #write mode reg MR3 with cs0. mww 0x63fd901c 0x00028031 ; #write mode reg MR1 with cs0. ODS=01: out buff= RZQ/7 (see below for settings) # out impedance = RZQ/7 # Rtt_nom disabled (no ODT at IO CMOS operation) # Aditive latency off # write leveling disabled # tdqs (differential?) disabled mww 0x63fd901c 0x09208030 ; #write mode reg MR0 with cs0 , with dll_rst0 mww 0x63fd901c 0x04008040 ; #ZQ calibration with cs0 (A10 high indicates ZQ cal long ZQCL) #********************************** # CS1: #********************************** # mww 0x63fd901c 0x0000803a ; #write mode reg MR2 with cs1. # mww 0x63fd901c 0x0000803b ; #write mode reg MR3 with cs1. # mww 0x63fd901c 0x00028039 ; #write mode reg MR1 with cs1. ODS=01: out buff= RZQ/7 # mww 0x63fd901c 0x09208138 ; #write mode reg MR0 with cs1. # mww 0x63fd901c 0x04008048 ; #ZQ calibration with cs1(A10 high indicates ZQ cal long ZQCL) #********************************** mww 0x63fd9020 0x00001800 ; # Refresh control register mww 0x63fd9040 0x04b80003 ; # ZQ HW control mww 0x63fd9058 0x00022227 ; # ODT control register mww 0x63fd901c 0x00000000 # CLKO muxing (comment out for now till needed to avoid conflicts with intended usage of signals) # mww 0x53FA8314 = 0 # mww 0x53FA8320 0x4 # mww 0x53FD4060 0x01e900f0 # dap apsel 0 } # IRAM $_TARGETNAME configure -work-area-phys 0xF8000000 -work-area-size 0x20000 -work-area-backup 1 flash bank mx535_nor cfi 0xf0000000 0x800000 2 2 $_TARGETNAME # vim:filetype=tcl