# SPDX-License-Identifier: GPL-2.0-or-later

# This is a stm32h735g-dk with a single STM32H735IGK6 chip.
# https://www.st.com/en/evaluation-tools/stm32h735g-dk.html
#

# This is for using the onboard STLINK
source [find interface/stlink.cfg]

transport select hla_swd

set CHIPNAME stm32h735igk6

# enable stmqspi
if {![info exists OCTOSPI1]} {
	set OCTOSPI1 1
	set OCTOSPI2 0
}

source [find target/stm32h7x.cfg]

reset_config srst_only

# OCTOSPI initialization
# octo: 8-line mode
proc octospi_init { octo } {
	global a b
	mmw 0x58024540 0x000006FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
	mmw 0x58024534 0x00284000 0				;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)
	sleep 1									;# Wait for clock startup

	mww 0x5200B404 0x03010111				;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1
	mww 0x5200B408 0x00000000				;# OCTOSPIM_P2CR: disable Port 2

	# PG06: OCSPI1_NCS, PF10: OCSPI1_CLK, PB02: OCSPI1_DQS, PD07: OCSPI1_IO7, PG09: OCSPI1_IO6, PD05: OCSPI1_IO5,
	# PD04: OCSPI1_IO4, PD13: OCSPI1_IO3, PE02: OCSPI1_IO2, PD12: OCSPI1_IO1, PD11: OCSPI1_IO0

	# PB02:AF10:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PD07:AF10:V, PD05:AF10:V
	# PD04:AF10:V, PE02:AF09:V, PF10:AF09:V, PG09:AF09:V, PG06:AF10:V
	# Port B: PB02:AF10:V
	mmw 0x58020400 0x00000020 0x00000010	;# MODER
	mmw 0x58020408 0x00000030 0x00000000	;# OSPEEDR
	mmw 0x5802040C 0x00000000 0x00000030	;# PUPDR
	mmw 0x58020420 0x00000A00 0x00000500	;# AFRL
	# Port D: PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
	mmw 0x58020C00 0x0A808A00 0x05404500	;# MODER
	mmw 0x58020C08 0x0FC0CF00 0x00000000	;# OSPEEDR
	mmw 0x58020C0C 0x00000000 0x0FC0CF00	;# PUPDR
	mmw 0x58020C20 0xA0AA0000 0x50550000	;# AFRL
	mmw 0x58020C24 0x00999000 0x00666000	;# AFRH
	# Port E: PE02:AF09:V
	mmw 0x58021000 0x00000020 0x00000010	;# MODER
	mmw 0x58021008 0x00000030 0x00000000	;# OSPEEDR
	mmw 0x5802100C 0x00000000 0x00000030	;# PUPDR
	mmw 0x58021020 0x00000900 0x00000600	;# AFRL
	# Port F: PF10:AF09:V
	mmw 0x58021400 0x00200000 0x00100000	;# MODER
	mmw 0x58021408 0x00300000 0x00000000	;# OSPEEDR
	mmw 0x5802140C 0x00000000 0x00300000	;# PUPDR
	mmw 0x58021424 0x00000900 0x00000600	;# AFRH
	# Port G: PG09:AF09:V, PG06:AF10:V
	mmw 0x58021800 0x00082000 0x00041000	;# MODER
	mmw 0x58021808 0x000C3000 0x00000000	;# OSPEEDR
	mmw 0x5802180C 0x00000000 0x000C3000	;# PUPDR
	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
	mmw 0x58021824 0x00000090 0x00000060	;# AFRH

	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
	mww 0x52005130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
	mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
	mww 0x52005008 0x01190100				;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
	mww 0x5200500C 0x00000005				;# OCTOSPI_DCR2: PRESCALER=5

	mww 0x52005108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
	mww 0x52005100 0x01003101				;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
	mww 0x52005110 0x00000013				;# OCTOSPI_IR: INSTR=READ4B

	flash probe $a							;# load configuration from CR, TCR, CCR, IR register values

	if { $octo == 1 } {
		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
		stmqspi cmd $a 0 0x06								;# Write Enable
		stmqspi cmd $a 1 0x05								;# Read Status Register
		stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02		;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable

		# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
		mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
		mww 0x52005108 0x10000006				;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
		mww 0x52005100 0x2C003C1C				;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
		mww 0x52005110 0x0000EE11				;# OCTOSPI_IR: INSTR=OCTA DTR Read

		flash probe $a							;# reload configuration from CR, TCR, CCR, IR register values

		stmqspi cmd $a 0 0x06								;# Write Enable
		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
		stmqspi cmd $a 0 0x04								;# Write Disable
		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
	}
}

$_CHIPNAME.cpu0 configure -event reset-init {
	global OCTOSPI1
	global OCTOSPI2

	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK

	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
	sleep 1
	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
	sleep 1

	adapter speed 24000

	if { $OCTOSPI1 } {
		octospi_init 1
	}
}