# Thanks to Pieter Conradie for this script! # # Unknown vendor board contains: # # Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz # OSCSEL configured for internal RC oscillator (22 to 42 kHz) # # 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit # 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks ################################################################## # We add to the minimal configuration. source [find target/at91sam9260.cfg] $_TARGETNAME configure -event reset-start { # At reset CPU runs at 22 to 42 kHz. # JTAG Frequency must be 6 times slower. jtag_rclk 3 halt # RSTC_MR : enable user reset, MMU may be enabled... use physical address mww phys 0xfffffd08 0xa5000501 } $_TARGETNAME configure -event reset-init { mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator sleep 20 ;# wait 20 ms mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator sleep 10 ;# wait 10 ms mww 0xfffffc28 0x205dbf09 ;# CKGR_PLLAR: Set PLLA Register for 192.512MHz sleep 20 ;# wait 20 ms mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2) sleep 10 ;# wait 10 ms mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (96.256 MHz) sleep 10 ;# wait 10 ms # Increase JTAG Speed to 6 MHz if RCLK is not supported jtag_rclk 6000 arm7_9 dcc_downloads enable ;# Enable faster DCC downloads mww 0xffffec00 0x01020102 ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit mww 0xffffec04 0x09070806 ;# SMC_PULSE0 mww 0xffffec08 0x000d000b ;# SMC_CYCLE0 mww 0xffffec0c 0x00001003 ;# SMC_MODE0 flash probe 0 ;# Identify flash bank 0 mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31 mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31 mww 0xfffff860 0xffff0000 ;# PIO_PUDR : Disable D15..D31 pull-ups mww 0xffffef1c 0x00010102 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM # VDDIOMSEL set for +3V3 memory # Disable D0..D15 pull-ups mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks) mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command mww 0x20000000 0 mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command mww 0x20000000 0 mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command mww 0x20000000 0 mww 0xffffea00 0x4 mww 0x20000000 0 mww 0xffffea00 0x4 mww 0x20000000 0 mww 0xffffea00 0x4 mww 0x20000000 0 mww 0xffffea00 0x4 mww 0x20000000 0 mww 0xffffea00 0x4 mww 0x20000000 0 mww 0xffffea00 0x4 mww 0x20000000 0 mww 0xffffea00 0x4 mww 0x20000000 0 mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command mww 0x20000000 0 mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode mww 0x20000000 0 mww 0xffffea04 0x2a2 ;# SDRAMC_TR : Set refresh timer count to 7us } ##################### # Flash configuration ##################### #flash bank cfi set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME