# SPDX-License-Identifier: GPL-2.0-or-later # Cadence virtual debug interface # Arm Cortex m4 through JTAG source [find interface/vdebug.cfg] set CHIPNAME m4 set MEMSTART 0x00000000 set MEMSIZE 0x10000 set CPUTAPID 0x4ba00477 # vdebug select transport transport select jtag # JTAG reset config, frequency and reset delay reset_config trst_and_srst adapter speed 25000 adapter srst delay 5 # BFM hierarchical path and input clk period vdebug bfm_path tbench.u_vd_jtag_bfm 20ns # DMA Memories to access backdoor (up to 20) vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $MEMSTART $MEMSIZE jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID jtag arp_init-reset source [find target/vd_cortex_m.cfg]