# # Configuration script for Arm CoreLink SSE-200 Subsystem based IoT SoCs. # global TARGET set TARGET $_CHIPNAME swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu # # SRAM on ARM CoreLink SSE-200 can be 4 banks of 8/16/32/64 KB # We will configure work area assuming 8-KB bank size in SRAM bank 1. # Also SRAM start addresses defaults to secure mode alias. # These values can be overridden as per board configuration # global _WORKAREASIZE_CPU0 if { [info exists WORKAREASIZE_CPU0] } { set _WORKAREASIZE_CPU0 $WORKAREASIZE_CPU0 } else { set _WORKAREASIZE_CPU0 0x1000 } global _WORKAREAADDR_CPU0 if { [info exists WORKAREAADDR_CPU0] } { set _WORKAREAADDR_CPU0 $WORKAREAADDR_CPU0 } else { set _WORKAREAADDR_CPU0 0x30008000 } # # Target configuration for Cortex M33 Core 0 on ARM CoreLink SSE-200 # Core 0 is the boot core and will always be configured. # target create ${TARGET}.CPU0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 ${TARGET}.CPU0 configure -work-area-phys $_WORKAREAADDR_CPU0 -work-area-size $_WORKAREASIZE_CPU0 -work-area-backup 0 ${TARGET}.CPU0 cortex_m reset_config sysresetreq # # Target configuration for Cortex M33 Core 1 on ARM CoreLink SSE-200 # Core 1 is optional and locked at boot until core 0 unlocks it. # if { $_ENABLE_CPU1 } { global _WORKAREASIZE_CPU1 if { [info exists WORKAREASIZE_CPU1] } { set _WORKAREASIZE_CPU1 $WORKAREASIZE_CPU1 } else { set _WORKAREASIZE_CPU1 0x1000 } global _WORKAREAADDR_CPU1 if { [info exists WORKAREAADDR_CPU1] } { set _WORKAREAADDR_CPU1 $WORKAREAADDR_CPU1 } else { set _WORKAREAADDR_CPU1 0x30009000 } target create ${TARGET}.CPU1 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1 ${TARGET}.CPU1 configure -work-area-phys $_WORKAREAADDR_CPU1 -work-area-size $_WORKAREASIZE_CPU1 -work-area-backup 0 ${TARGET}.CPU1 cortex_m reset_config vectreset } # Make sure the default target is the boot core targets ${TARGET}.CPU0