#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst

if { [info exists CHIPNAME] } {	
   set  _CHIPNAME $CHIPNAME    
} else {	 
   set  _CHIPNAME imx27
}

if { [info exists ENDIAN] } {	
   set  _ENDIAN $ENDIAN    
} else {	 
   set  _ENDIAN little
}


# Note above there are 2 taps 

# The bs tap
if { [info exists BSTAPID ] } {
   set _BSTAPID $BSTAPID
} else {
   set _BSTAPID 0x1b900f0f
}
jtag newtap $_CHIPNAME bs  -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_BSTAPID

# The CPU tap
if { [info exists CPUTAPID ] } {
   set _CPUTAPID $CPUTAPID
} else {
   set _CPUTAPID 0x07926121
}
jtag newtap $_CHIPNAME cpu  -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID

# Create the GDB Target.
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 -work-area-size  0x8000 -work-area-backup 1
# Internal to the chip, there is 45K of SRAM
#

arm7_9 dcc_downloads enable