# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME lpc1768 } if { [info exists ENDIAN] } { set _ENDIAN $ENDIAN } else { set _ENDIAN little } if { [info exists CPUTAPID ] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x4ba00477 } #delays on reset lines jtag_nsrst_delay 200 jtag_ntrst_delay 200 # LPC2000 & LPC1700 -> SRST causes TRST reset_config trst_and_srst srst_pulls_trst jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME # LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM) $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0 $_TARGETNAME configure -event reset-init { # Force target into ARM state armv4_5 core_state arm #do not remap 0x0000-0x0020 to anything but the flash # mwb 0xE01FC040 0x01 mwb 0xE000ED08 0x00 } # LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region). # flash bank lpc1700 0 0 [calc_checksum] flash bank lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 12000 calc_checksum # 4MHz / 6 = 666kHz, so use 500 jtag_khz 500