# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME lpc1768 } # After reset the chip is clocked by the ~4MHz internal RC oscillator. # When board-specific code (reset-init handler or device firmware) # configures another oscillator and/or PLL0, set CCLK to match; if # you don't, then flash erase and write operations may misbehave. # (The ROM code doing those updates cares about core clock speed...) # # CCLK is the core clock frequency in KHz if { [info exists CCLK ] } { set _CCLK $CCLK } else { set _CCLK 4000 } if { [info exists CPUTAPID ] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x4ba00477 } #delays on reset lines adapter_nsrst_delay 200 jtag_ntrst_delay 200 # LPC2000 & LPC1700 -> SRST causes TRST reset_config srst_pulls_trst jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME # LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000) # and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000). $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 # LPC1768 has 512kB of flash memory, managed by ROM code (including a # boot loader which verifies the flash exception table's checksum). set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \ lpc1700 $_CCLK calc_checksum # JTAG clock should be CCLK/6 (unless using adaptive clocking) # CCLK is 4 MHz after reset, and until board-specific code (like # a reset-init handler) speeds it up. jtag_rclk [ expr 4000 / 6 ] $_TARGETNAME configure -event reset-start { jtag_rclk [ expr 4000 / 6] }