# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,

# LPC17xx chips support both JTAG and SWD transports.
# Adapt based on what transport is active.
source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
	set  _CHIPNAME $CHIPNAME
} else {
	set  _CHIPNAME lpc1768
}

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
if { [info exists CCLK ] } {
	set _CCLK $CCLK
} else {
	set _CCLK 4000
}
if { [info exists CPUTAPID ] } {
	set _CPUTAPID $CPUTAPID
} else {
	set _CPUTAPID 0x4ba00477
}

#delays on reset lines
adapter_nsrst_delay 200
jtag_ntrst_delay 200

#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME

# LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000

# LPC1768 has 512kB of flash memory, managed by ROM code (including a
# boot loader which verifies the flash exception table's checksum).
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
	lpc1700 $_CCLK calc_checksum

# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
jtag_khz 10

$_TARGETNAME configure -event reset-init {
	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
	# "User Flash Mode" where interrupt vectors are _not_ remapped,
	# and reside in flash instead).
	#
	# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
	# Bit Symbol Value Description Reset
	# value
	# 0 MAP Memory map control. 0
	# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
	# 1 User mode. The on-chip Flash memory is mapped to address 0.
	# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
	#
	# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user

	mww 0x400FC040 0x01
}