# # NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each # adapter speed 500 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME lpc4370 } # # M4 JTAG mode TAP # if { [info exists M4_JTAG_TAPID] } { set _M4_JTAG_TAPID $M4_JTAG_TAPID } else { set _M4_JTAG_TAPID 0x4ba00477 } # # M4 SWD mode TAP # if { [info exists M4_SWD_TAPID] } { set _M4_SWD_TAPID $M4_SWD_TAPID } else { set _M4_SWD_TAPID 0x2ba01477 } source [find target/swj-dp.tcl] if { [using_jtag] } { set _M4_TAPID $_M4_JTAG_TAPID } else { set _M4_TAPID $_M4_SWD_TAPID } # # M0 TAP # if { [info exists M0_JTAG_TAPID] } { set _M0_JTAG_TAPID $M0_JTAG_TAPID } else { set _M0_JTAG_TAPID 0x0ba01477 } swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_M4_TAPID dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4 target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap # LPC4370 has 96+32 KB contiguous SRAM if { [info exists WORKAREASIZE] } { set _WORKAREASIZE $WORKAREASIZE } else { set _WORKAREASIZE 0x20000 } $_CHIPNAME.m4 configure -work-area-phys 0x10000000 \ -work-area-size $_WORKAREASIZE -work-area-backup 0 if { [using_jtag] } { jtag newtap $_CHIPNAME m0app -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_M0_JTAG_TAPID jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_M0_JTAG_TAPID dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap # 32+8+32 KB SRAM $_CHIPNAME.m0app configure -work-area-phys 0x10080000 \ -work-area-size 0x92000 -work-area-backup 0 # 16+2 KB M0 subsystem SRAM $_CHIPNAME.m0sub configure -work-area-phys 0x18000000 \ -work-area-size 0x4800 -work-area-backup 0 # Default to the Cortex-M4 targets $_CHIPNAME.m4 } if { ![using_hla] } { cortex_m reset_config vectreset }