# SPDX-License-Identifier: GPL-2.0-or-later # NXP LPC8Nxx NHS31xx Cortex-M0+ with 8kB SRAM # Copyright (C) 2018 by Jean-Christian de Rivaz # Based on NXP proposal https://community.nxp.com/message/1011149 # Many thanks to Dries Moors from NXP support. # SWD only transport source [find target/swj-dp.tcl] source [find mem_helper.tcl] if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME lpc8nxx } swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id 0 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap if {![using_hla]} { # If srst is not fitted use SYSRESETREQ to perform a soft reset cortex_m reset_config sysresetreq } adapter srst delay 100 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0 flash bank $_CHIPNAME.flash lpc2000 0x0 0x7800 0 0 $_TARGETNAME lpc800 500 echo "*********************************************************************************" echo "* !!!!! IMPORTANT NOTICE FOR LPC8Nxx and NHS31xx CHIPS !!!!!" echo "* When this IC is in power-off or peep power down mode, the SWD HW block is also" echo "* unpowered. These modes can be entered by firmware. The default firmware image" echo "* (flashed in production) makes use of this. Best is to avoid these power modes" echo "* during development, and only later add them when the functionality is complete." echo "* Hardware reset or NFC field are the only ways to connect in case the SWD is" echo "* powered off. OpenOCD can do a hardware reset if you wire the adapter SRST" echo "* signal to the chip RESETN pin and add the following in your configuration:" echo "* reset_config srst_only; flash init; catch init; reset" echo "* But if the actual firmware immediately set the power down mode after reset," echo "* OpenOCD might be not fast enough to halt the CPU before the SWD lost power. In" echo "* that case the only solution is to apply a NFC field to keep the SWD powered." echo "*********************************************************************************" # Using soft-reset 'reset_config none' is strongly discouraged. # RESETN sets the system clock to 500 kHz. Unlike soft-reset does not. # Set the system clock to 500 kHz before reset to simulate the functionality of hw reset. # proc set_sysclk_500khz {} { set SYSCLKCTRL 0x40048020 set SYSCLKUEN 0x40048024 mww $SYSCLKUEN 0 mmw $SYSCLKCTRL 0x8 0xe mww $SYSCLKUEN 1 echo "Notice: sysclock set to 500kHz." } # Do not remap the ARM interrupt vectors to anything but the beginning of the flash. # Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description # Bit Symbol Value Description # 0 map - interrupt vector remap. 0 after boot. # 0 interrupt vector reside in Flash # 1 interrupt vector reside in SRAM # 5:1 offset - system memory remap offset. 00000b after boot. # 00000b interrupt vectors in flash or remapped to SRAM but no offset # 00001b - # 00111b interrupt vectors offset in flash or SRAM to 1K word segment # 01000b - # 11111b interrupt vectors offset in flash to 1K word segment 8 to 31 # 31:6 reserved # proc set_no_remap {} { mww 0x40048000 0x00 echo "Notice: interrupt vector set to no remap." } $_TARGETNAME configure -event reset-init { set_sysclk_500khz set_no_remap }