@insertcopying
@menu
-* About:: About OpenOCD.
-* Developers:: OpenOCD developers
-* Building:: Building OpenOCD
+* About:: About OpenOCD
+* Developers:: OpenOCD Developers
+* Building OpenOCD:: Building OpenOCD From SVN
* JTAG Hardware Dongles:: JTAG Hardware Dongles
* Running:: Running OpenOCD
* Simple Configuration Files:: Simple Configuration Files
* Tap Creation:: Tap Creation
* Target Configuration:: Target Configuration
* Flash Configuration:: Flash Configuration
+* NAND Flash Commands:: NAND Flash Commands
* General Commands:: General Commands
* JTAG Commands:: JTAG Commands
* Sample Scripts:: Sample Target Scripts
* TFTP:: TFTP
* GDB and OpenOCD:: Using GDB and OpenOCD
-* Tcl scripting API:: Tcl scripting API
+* Tcl Scripting API:: Tcl Scripting API
* Upgrading:: Deprecated/Removed Commands
-* Target library:: Target library
+* Target Library:: Target Library
* FAQ:: Frequently Asked Questions
* Tcl Crash Course:: Tcl Crash Course
* License:: GNU Free Documentation License
@comment case issue with ``Index.html'' and ``index.html''
@comment Occurs when creating ``--html --no-split'' output
@comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
-* OpenOCD Index:: Main index.
+* OpenOCD Concept Index:: Concept Index
+* OpenOCD Command Index:: Command Index
@end menu
@node About
@unnumbered About
@cindex about
+OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
+University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
+Since that time, the project has grown into an active open-source project,
+supported by a diverse community of software and hardware developers from
+around the world.
+
+@section What is OpenOCD?
+
The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
in-system programming and boundary-scan testing for embedded target
devices.
with the JTAG (IEEE 1149.1) compliant taps on your target board.
@b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
-Based, Parallel Port Based, and other standalone boxes that run
-OpenOCD internally. See the section titled: @xref{JTAG Hardware Dongles}.
+based, parallel port based, and other standalone boxes that run
+OpenOCD internally. @xref{JTAG Hardware Dongles}.
@b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be
-debugged via the GDB Protocol.
+debugged via the GDB protocol.
@b{Flash Programing:} Flash writing is supported for external CFI
-compatible flashes (Intel and AMD/Spansion command set) and several
-internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3 and
-STM32x). Preliminary support for using the LPC3180's NAND flash
-controller is included.
+compatible NOR flashes (Intel and AMD/Spansion command set) and several
+internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and
+STM32x). Preliminary support for various NAND flash controllers
+(LPC3180, Orion, S3C24xx, more) controller is included.
+
+@section OpenOCD Web Site
+
+The OpenOCD web site provides the latest public news from the community:
+
+@uref{http://openocd.berlios.de/web/}
+
@node Developers
-@chapter Developers
+@chapter OpenOCD Developer Resources
@cindex developers
-OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
-University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
-Others interested in improving the state of free and open debug and testing technology
-are welcome to participate.
+If you are interested in improving the state of OpenOCD's debugging and
+testing support, new contributions will be welcome. Motivated developers
+can produce new target, flash or interface drivers, improve the
+documentation, as well as more conventional bug fixes and enhancements.
+
+The resources in this chapter are available for developers wishing to explore
+or expand the OpenOCD source code.
+
+@section OpenOCD Subversion Repository
+
+The ``Building From Source'' section provides instructions to retrieve
+and and build the latest version of the OpenOCD source code.
+@xref{Building OpenOCD}.
+
+Developers that want to contribute patches to the OpenOCD system are
+@b{strongly} encouraged to base their work off of the most recent trunk
+revision. Patches created against older versions may require additional
+work from their submitter in order to be updated for newer releases.
+
+@section Doxygen Developer Manual
+
+During the development of the 0.2.0 release, the OpenOCD project began
+providing a Doxygen reference manual. This document contains more
+technical information about the software internals, development
+processes, and similar documentation:
+
+@uref{http://openocd.berlios.de/doc/doxygen/index.html}
+
+This document is a work-in-progress, but contributions would be welcome
+to fill in the gaps. All of the source files are provided in-tree,
+listed in the Doxyfile configuration in the top of the repository trunk.
+
+@section OpenOCD Developer Mailing List
-Other developers have contributed support for additional targets and flashes as well
-as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
+The OpenOCD Developer Mailing List provides the primary means of
+communication between developers:
-The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
+ @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
-@node Building
-@chapter Building
-@cindex building OpenOCD
+All drivers developers are enouraged to also subscribe to the list of
+SVN commits to keep pace with the ongoing changes:
+
+ @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
+
+@node Building OpenOCD
+@chapter Building OpenOCD
+@cindex building
@section Pre-Built Tools
If you are interested in getting actual work done rather than building
@section Packagers Please Read!
-If you are a @b{PACKAGER} of OpenOCD if you
+You are a @b{PACKAGER} of OpenOCD if you
@enumerate
@item @b{Sell dongles} and include pre-built binaries
@item @b{Build packages} i.e.: RPM files, or DEB files for a Linux Distro
@end enumerate
-As a @b{PACKAGER} - you are at the top of the food chain. You solve
-problems for downstream users. What you fix or solve - solves hundreds
-if not thousands of user questions. If something does not work for you
-please let us know. That said, would also like you to follow a few
+As a @b{PACKAGER}, you will experience first reports of most issues.
+When you fix those problems for your users, your solution may help
+prevent hundreds (if not thousands) of other questions from other users.
+
+If something does not work for you, please work to inform the OpenOCD
+developers know how to improve the system or documentation to avoid
+future problems, and follow-up to help us ensure the issue will be fully
+resolved in our future releases.
+
+That said, the OpenOCD developers would also like you to follow a few
suggestions:
@enumerate
-@item @b{Always build with printer ports enabled}.
-@item @b{Try to use LIBFTDI + LIBUSB where possible}. You cover more bases.
+@item @b{Always build with printer ports enabled.}
+@item @b{Try to use LIBFTDI + LIBUSB where possible. You cover more bases.}
@end enumerate
-It is your decision..
-
@itemize @bullet
-@item @b{Why YES to LIBFTDI + LIBUSB}
+@item @b{Why YES to LIBFTDI + LIBUSB?}
@itemize @bullet
@item @b{LESS} work - libusb perhaps already there
-@item @b{LESS} work - identical code multiple platforms
+@item @b{LESS} work - identical code, multiple platforms
@item @b{MORE} dongles are supported
@item @b{MORE} platforms are supported
@item @b{MORE} complete solution
@end itemize
-@item @b{Why not LIBFTDI + LIBUSB} (i.e.: ftd2xx instead)
+@item @b{Why not LIBFTDI + LIBUSB} (i.e.: ftd2xx instead)?
@itemize @bullet
-@item @b{LESS} Some say it is slower.
+@item @b{LESS} speed - some say it is slower
@item @b{LESS} complex to distribute (external dependencies)
@end itemize
@end itemize
@section Building From Source
-You can download the current SVN version with SVN client of your choice from the
+You can download the current SVN version with an SVN client of your choice from the
following repositories:
- (@uref{svn://svn.berlios.de/openocd/trunk})
+ @uref{svn://svn.berlios.de/openocd/trunk}
or
- (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
+ @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
Using the SVN command line client, you can use the following command to fetch the
latest version (make sure there is no (non-svn) directory called "openocd" in the
svn checkout svn://svn.berlios.de/openocd/trunk openocd
@end example
-Building OpenOCD requires a recent version of the GNU autotools.
-On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
+Building OpenOCD requires a recent version of the GNU autotools (autoconf >= 2.59 and automake >= 1.9).
+For building on Windows,
you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
paths, resulting in obscure dependency errors (This is an observation I've gathered
You further need the appropriate driver files, if you want to build support for
a FTDI FT2232 based interface:
+
@itemize @bullet
@item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
@item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
@item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
-homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
+homepage (@uref{http://www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
@end itemize
-libftdi is supported under Windows. Do not use versions earlier then 0.14.
+libftdi is supported under Windows. Do not use versions earlier than 0.14.
In general, the D2XX driver provides superior performance (several times as fast),
but has the draw-back of being binary-only - though that isn't that bad, as it isn't
a kernel module, only a user space library.
To build OpenOCD (on both Linux and Cygwin), use the following commands:
+
@example
./bootstrap
@end example
+
Bootstrap generates the configure script, and prepares building on your system.
+
@example
./configure [options, see below]
@end example
+
Configure generates the Makefiles used to build OpenOCD.
+
@example
make
make install
@end example
+
Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.
The configure script takes several options, specifying which JTAG interfaces
-should be included:
+should be included (among other things):
@itemize @bullet
@item
-@option{--enable-parport} - Bit bang pc printer ports.
+@option{--enable-parport} - Enable building the PC parallel port driver.
+@item
+@option{--enable-parport_ppdev} - Enable use of ppdev (/dev/parportN) for parport.
+@item
+@option{--enable-parport_giveio} - Enable use of giveio for parport instead of ioperm.
+@item
+@option{--enable-amtjtagaccel} - Enable building the Amontec JTAG-Accelerator driver.
@item
-@option{--enable-parport_ppdev} - Parallel Port [see below]
+@option{--enable-ecosboard} - Enable building support for eCosBoard based JTAG debugger.
@item
-@option{--enable-parport_giveio} - Parallel Port [see below]
+@option{--enable-ioutil} - Enable ioutil functions - useful for standalone OpenOCD implementations.
@item
-@option{--enable-amtjtagaccel} - Parallel Port [Amontec, see below]
+@option{--enable-httpd} - Enable builtin httpd server - useful for standalone OpenOCD implementations.
@item
-@option{--enable-ft2232_ftd2xx} - Numerous USB Type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).
+@option{--enable-ep93xx} - Enable building support for EP93xx based SBCs.
@item
-@option{--enable-ft2232_libftdi} - An open source (free) alternate to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin)
+@option{--enable-at91rm9200} - Enable building support for AT91RM9200 based SBCs.
+@item
+@option{--enable-gw16012} - Enable building support for the Gateworks GW16012 JTAG programmer.
+@item
+@option{--enable-ft2232_ftd2xx} - Numerous USB type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).
+@item
+@option{--enable-ft2232_libftdi} - An open source (free) alternative to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin).
@item
@option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c, point at the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
@item
-@option{--with-ftd2xx-linux-tardir=PATH} - Linux only equal of @option{--with-ftd2xx-win32-zipdir}, where you unpacked the TAR.GZ file.
+@option{--with-ftd2xx-linux-tardir=PATH} - Linux only. Equivalent of @option{--with-ftd2xx-win32-zipdir}, where you unpacked the TAR.GZ file.
+@item
+@option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static. Specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. The 'shared' value is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
@item
-@option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static, specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. Shared is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
+@option{--enable-presto_libftdi} - Enable building support for ASIX Presto programmer using the libftdi driver.
@item
-@option{--enable-gw16012}
+@option{--enable-presto_ftd2xx} - Enable building support for ASIX Presto programmer using the FTD2XX driver.
@item
-@option{--enable-usbprog}
+@option{--enable-usbprog} - Enable building support for the USBprog JTAG programmer.
@item
-@option{--enable-presto_libftdi}
+@option{--enable-oocd_trace} - Enable building support for the OpenOCD+trace ETM capture device.
@item
-@option{--enable-presto_ftd2xx}
+@option{--enable-jlink} - Enable building support for the Segger J-Link JTAG programmer.
@item
-@option{--enable-jlink} - From SEGGER
+@option{--enable-vsllink} - Enable building support for the Versaloon-Link JTAG programmer.
@item
-@option{--enable-vsllink}
+@option{--enable-rlink} - Enable building support for the Raisonance RLink JTAG programmer.
@item
-@option{--enable-rlink} - Raisonance.com dongle.
+@option{--enable-arm-jtag-ew} - Enable building support for the Olimex ARM-JTAG-EW programmer.
@item
-@option{--enable-arm-jtag-ew} - Olimex ARM-JTAG-EW dongle.
+@option{--enable-dummy} - Enable building the dummy port driver.
@end itemize
@section Parallel Port Dongles
the @option{--enable-parport_ppdev} option actually is an option to the parport driver
(see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
+The same is true for the @option{--enable-parport_giveio} option, you have to
+use both the @option{--enable-parport} AND the @option{--enable-parport_giveio} option if you want to use giveio instead of ioperm parallel port access method.
+
@section FT2232C Based USB Dongles
There are 2 methods of using the FTD2232, either (1) using the
1) Check out the latest version of ``openocd'' from SVN.
-2) Download & Unpack either the Windows or Linux FTD2xx Drivers
- (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
+2) Download & unpack either the Windows or Linux FTD2xx drivers
+ (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
@example
/home/duane/ftd2xx.win32 => the Cygwin/Win32 ZIP file contents.
- /home/duane/libftd2xx0.4.16 => the Linux TAR file contents.
+ /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents.
@end example
3) Configure with these options:
@example
-Cygwin FTCICHIP solution
- ./configure --prefix=/home/duane/mytools \
- --enable-ft2232_ftd2xx \
- --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
+Cygwin FTDICHIP solution:
+ ./configure --prefix=/home/duane/mytools \
+ --enable-ft2232_ftd2xx \
+ --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
-Linux FTDICHIP solution
+Linux FTDICHIP solution:
./configure --prefix=/home/duane/mytools \
- --enable-ft2232_ftd2xx \
- --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
+ --enable-ft2232_ftd2xx \
+ --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
-Cygwin/Linux LIBFTDI solution
+Cygwin/Linux LIBFTDI solution:
Assumes:
1a) For Windows: The Windows port of LIBUSB is in place.
- 1b) For Linux: libusb has been built and is inplace.
+ 1b) For Linux: libusb has been built/installed and is in place.
2) And libftdi has been built and installed
Note: libftdi - relies upon libusb.
./configure --prefix=/home/duane/mytools \
- --enable-ft2232_libftdi
+ --enable-ft2232_libftdi
@end example
4) Then just type ``make'', and perhaps ``make install''.
-@section Miscellaneous configure options
+@section Miscellaneous Configure Options
@itemize @bullet
@item
-@option{--enable-gccwarnings} - enable extra gcc warnings during build.
+@option{--disable-option-checking} - Ignore unrecognized @option{--enable} and @option{--with} options.
+@item
+@option{--enable-gccwarnings} - Enable extra gcc warnings during build.
Default is enabled.
@item
-@option{--enable-release} - enable building of a openocd release, generally
+@option{--enable-release} - Enable building of an OpenOCD release, generally
this is for developers. It simply omits the svn version string when the
openocd @option{-v} is executed.
@end itemize
@cindex wiggler
@cindex zy1000
@cindex printer port
-@cindex USB adapter
+@cindex USB Adapter
@cindex rtck
Defined: @b{dongle}: A small device that plugins into a computer and serves as
In the OpenOCD case, this generally refers to @b{a small adapater} one
attaches to your computer via USB or the Parallel Printer Port. The
execption being the Zylin ZY1000 which is a small box you attach via
-an ethernet cable.
+an ethernet cable. The Zylin ZY1000 has the advantage that it does not
+require any drivers to be installed on the developer PC. It also has
+a built in web interface. It supports RTCK/RCLK or adaptive clocking
+and has a built in relay to power cycle targets remotely.
@section Choosing a Dongle
@section Stand alone Systems
@b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
-dongle, but a standalone box.
+dongle, but a standalone box. The ZY1000 has the advantage that it does
+not require any drivers installed on the developer PC. It also has
+a built in web interface. It supports RTCK/RCLK or adaptive clocking
+and has a built in relay to power cycle targets remotely.
@section USB FT2232 Based
Some key things you should look at and understand are:
@enumerate
-@item The RESET configuration of your debug environment as a whole
+@item The reset configuration of your debug environment as a whole
@item Is there a ``work area'' that OpenOCD can use?
@* For ARM - work areas mean up to 10x faster downloads.
@item For MMU/MPU based ARM chips (i.e.: ARM9 and later) will that work area still be available?
In summary the board files should contain (if present)
@enumerate
-@item External flash configuration (i.e.: the flash on CS0)
+@item External flash configuration (i.e.: NOR flash on CS0, two NANDs on CS2)
@item SDRAM configuration (size, speed, etc.
@item Board specific IO configuration (i.e.: GPIO pins might disable a 2nd flash)
@item Multiple TARGET source statements
In summary the target files should contain
@enumerate
-@item Set Defaults
-@item Create Taps
-@item Reset Configuration
-@item Work Areas
-@item CPU/Chip/CPU-Core Specific features
-@item OnChip Flash
+@item Set defaults
+@item Create taps
+@item Reset configuration
+@item Work areas
+@item CPU/Chip/CPU-Core specific features
+@item On-Chip flash
@end enumerate
@subsection Important variable names
At no time should the name ``target0'' (the default target name if
none was specified) be used. The name ``target0'' is a hard coded name
- the next target on the board will be some other number.
+In the same way, avoid using target numbers even when they are
+permitted; use the right target name(s) for your board.
The user (or board file) should reasonably be able to:
@item @b{cpu}
@item @b{flash}
@item @b{bs}
+@item @b{etb}
@item @b{jrc}
@item @b{unknownN} - it happens :-(
@end itemize
If present, the MMU, the MPU and the CACHE should be disabled.
+Some ARM cores are equipped with trace support, which permits
+examination of the instruction and data bus activity. Trace
+activity is controlled through an ``Embedded Trace Module'' (ETM)
+on one of the core's scan chains. The ETM emits voluminous data
+through a ``trace port''. The trace port is accessed in one
+of two ways. When its signals are pinned out from the chip,
+boards may provide a special high speed debugging connector;
+software support for this is not configured by default, use
+the ``--enable-oocd_trace'' option. Alternatively, trace data
+may be stored an on-chip SRAM which is packaged as an ``Embedded
+Trace Buffer'' (ETB). An ETB has its own TAP, usually right after
+its associated ARM core. OpenOCD supports the ETM, and your
+target configuration should set it up with the relevant trace
+port: ``etb'' for chips which use that, else the board-specific
+option will be either ``oocd_trace'' or ``dummy''.
+
+@example
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
+@end example
+
@subsection Internal Flash Configuration
This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
@b{Never ever} in the ``target configuration file'' define any type of
-flash that is external to the chip. (For example the BOOT flash on
-Chip Select 0). The BOOT flash information goes in a board file - not
+flash that is external to the chip. (For example a BOOT flash on
+Chip Select 0.) Such flash information goes in a board file - not
the TARGET (chip) file.
Examples:
@item @b{Historical Note}
@* JIM-Tcl was introduced to OpenOCD in spring 2008.
-@item @b{Need a Crash Course In Tcl?}
+@item @b{Need a crash course in Tcl?}
@* See: @xref{Tcl Crash Course}.
@end itemize
openocd.cfg file to force OpenOCD to ``initialize'' and make the
targets ready. For example: If your openocd.cfg file needs to
read/write memory on your target - the init command must occur before
-the memory read/write commands.
+the memory read/write commands. This includes @command{nand probe}.
@section TCP/IP Ports
@itemize @bullet
@*Force breakpoint type for gdb 'break' commands.
The raison d'etre for this option is to support GDB GUI's without
a hard/soft breakpoint concept where the default OpenOCD and
-GDB behavior is not sufficient. Note that GDB will use hardware
+GDB behaviour is not sufficient. Note that GDB will use hardware
breakpoints if the memory map has been set up for flash regions.
This option replaces older arm7_9 target commands that addressed
@item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
@cindex gdb_detach
@*Configures what OpenOCD will do when GDB detaches from the daemon.
-Default behavior is <@var{resume}>
+Default behaviour is <@var{resume}>
@item @b{gdb_memory_map} <@var{enable|disable}>
@cindex gdb_memory_map
requested. GDB will then know when to set hardware breakpoints, and program flash
using the GDB load command. @option{gdb_flash_program enable} must also be enabled
for flash programming to work.
-Default behavior is <@var{enable}>
+Default behaviour is <@var{enable}>
@xref{gdb_flash_program}.
@item @b{gdb_flash_program} <@var{enable|disable}>
@anchor{gdb_flash_program}
@*Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
vFlash packet is received.
-Default behavior is <@var{enable}>
+Default behaviour is <@var{enable}>
@comment END GDB Items
@end itemize
It is debatable if this command belongs here - or in a board
configuration file. In fact, in some situations the JTAG speed is
-changed during the target initialization process (i.e.: (1) slow at
+changed during the target initialisation process (i.e.: (1) slow at
reset, (2) program the CPU clocks, (3) run fast)
Speed 0 (khz) selects RTCK method. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
support the rate asked for, or can not translate from kHz to
jtag_speed, then an error is returned.
-Make sure the JTAG clock is no more than @math{1/6th × CPU-Clock}. This is
+Make sure the JTAG clock is no more than @math{1/6th CPU-Clock}. This is
especially true for synthesized cores (-S). Also see RTCK.
@b{NOTE: Script writers} If the target chip requires/uses RTCK -
@node Reset Configuration
@chapter Reset Configuration
-@cindex reset configuration
+@cindex Reset Configuration
Every system configuration may require a different reset
configuration. This can also be quite confusing. Please see the
@section reset_config
-@b{Note:} To maintainer and integrators: Where exactly the
+@b{Note:} To maintainers and integrators: Where exactly the
``reset configuration'' goes is a good question. It touches several
things at once. In the end, if you have a board file - the board file
should define it and assume 100% that the DONGLE supports
the system is reset together with the test logic (only hypothetical, I
haven't seen hardware with such a bug, and can be worked around).
@option{combined} implies both @option{srst_pulls_trst} and
-@option{trst_pulls_srst}. The default behavior if no option given is
+@option{trst_pulls_srst}. The default behaviour if no option given is
@option{separate}.
The [@var{trst_type}] and [@var{srst_type}] parameters allow the
Tap Uses:
@itemize @bullet
@item @b{Debug Target} A tap can be used by a GDB debug target
-@item @b{Flash Programing} Some chips program the flash via JTAG
+@item @b{Flash Programing} Some chips program the flash directly via JTAG,
+instead of indirectly by making a CPU do it.
@item @b{Boundry Scan} Some chips support boundary scan.
@end itemize
the size of the IR.
@comment END REQUIRED
@end itemize
-An example of a FOOBAR tap
+An example of a FOOBAR Tap
@example
jtag newtap foobar tap -irlen 7 -ircapture 0x42 -irmask 0x55
@end example
@itemize @bullet
@item @b{-expected-id NUMBER}
@* By default it is zero. If non-zero represents the
-expected tap ID used when the JTAG chain is examined. See below.
+expected tap ID used when the JTAG chain is examined. Repeat
+the option as many times as required if multiple id's can be
+expected. See below.
@item @b{-disable}
@item @b{-enable}
@* By default not specified the tap is enabled. Some chips have a
@item @b{cpu} - the main CPU of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
@item @b{flash} - if the chip has a flash tap, example: str912.flash
@item @b{bs} - for boundary scan if this is a seperate tap.
+@item @b{etb} - for an embedded trace buffer (example: an ARM ETB11)
@item @b{jrc} - for JTAG route controller (example: OMAP3530 found on Beagleboards)
@item @b{unknownN} - where N is a number if you have no idea what the tap is for
@item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
@item @b{Note: Deprecated} - Index Numbers
@* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
feature is still present, however its use is highly discouraged and
-should not be counted upon.
+should not be counted upon. Update all of your scripts to use
+TAP names rather than numbers.
@item @b{Multiple chips}
@* If your board has multiple chips, you should be
able to @b{source} two configuration files, in the proper order, and
The ``standard way'' to remove a tap would be to place the tap in
bypass mode. But with the advent of modern chips, this is not always a
good solution. Some taps operate slowly, others operate fast, and
-there are other JTAG clock synchronization problems one must face. To
+there are other JTAG clock synchronisation problems one must face. To
solve that problem, the JTAG route controller was introduced. Rather
than ``bypass'' the tap, the tap is completely removed from the
circuit and skipped.
@item @b{reset-halt-pre}
@* Currently not used
@item @b{reset-init}
-@* Currently not used
+@* Used by @b{reset init} command for board-specific initialization.
+This is where you would configure PLLs and clocking, set up DRAM so
+you can download programs that don't fit in on-chip SRAM, set up pin
+multiplexing, and so on.
@item @b{reset-start}
@* Currently not used
@item @b{reset-wait-pos}
@end example
@end itemize
-
@section target create
@cindex target
@cindex target creation
@itemize @bullet
@item @b{NAME}
@* Is the name of the debug target. By convention it should be the tap
-DOTTED.NAME, this name is also used to create the target object
-command.
+DOTTED.NAME. This name is also used to create the target object
+command, and in other places the target needs to be identified.
@item @b{TYPE}
@* Specifies the target type, i.e.: ARM7TDMI, or Cortex-M3. Currently supported targets are:
@comment START types
@section Target Config/Cget Options
These options can be specified when the target is created, or later
via the configure option or to query the target via cget.
+
+You should specify a working area if you can; typically it uses some
+on-chip SRAM. Such a working area can speed up many things, including bulk
+writes to target memory; flash operations like checking to see if memory needs
+to be erased; GDB memory checksumming; and may help perform otherwise
+unavailable operations (like some coprocessor operations on ARM7/9 systems).
@itemize @bullet
@item @b{-type} - returns the target type
@item @b{-event NAME BODY} see Target events
-@item @b{-work-area-virt [ADDRESS]} specify/set the work area
-@item @b{-work-area-phys [ADDRESS]} specify/set the work area
+@item @b{-work-area-virt [ADDRESS]} specify/set the work area base address
+which will be used when an MMU is active.
+@item @b{-work-area-phys [ADDRESS]} specify/set the work area base address
+which will be used when an MMU is inactive.
@item @b{-work-area-size [ADDRESS]} specify/set the work area
-@item @b{-work-area-backup [0|1]} does the work area get backed up
+@item @b{-work-area-backup [0|1]} does the work area get backed up;
+by default, it doesn't. When possible, use a working_area that doesn't
+need to be backed up, since performing a backup slows down operations.
@item @b{-endian [big|little]}
@item @b{-variant [NAME]} some chips have variants OpenOCD needs to know about
@item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
@* use variant <@var{-variant lm3s}> when debugging Luminary lm3s targets. This will cause
OpenOCD to use a software reset rather than asserting SRST to avoid a issue with clearing
the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
-be detected and the normal reset behavior used.
+be detected and the normal reset behaviour used.
@item @b{xscale}
@* Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},@option{pxa250}, @option{pxa255}, @option{pxa26x}.
@item @b{arm11}
@end example
@* The target# is a the 0 based target numerical index.
-This command specifies a working area for the debugger to use. This
-may be used to speed-up downloads to target memory and flash
-operations, or to perform otherwise unavailable operations (some
-coprocessor operations on ARM7/9 systems, for example). The last
-parameter decides whether the memory should be preserved
-(<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If
-possible, use a working_area that doesn't need to be backed up, as
-performing a backup slows down operation.
-
@node Flash Configuration
-@chapter Flash Programing
+@chapter Flash programming
@cindex Flash Configuration
+OpenOCD has different commands for NOR and NAND flash;
+the ``flash'' command works with NOR flash, while
+the ``nand'' command works with NAND flash.
+This partially reflects different hardware technologies:
+NOR flash usually supports direct CPU instruction and data bus access,
+while data from a NAND flash must be copied to memory before it can be
+used. (SPI flash must also be copied to memory before use.)
+However, the documentation also uses ``flash'' as a generic term;
+for example, ``Put flash configuration in board-specific files''.
+
@b{Note:} As of 28/nov/2008 OpenOCD does not know how to program a SPI
flash that a micro may boot from. Perhaps you, the reader, would like to
contribute support for this.
@example
@b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
-<@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
+<@var{bus_width}> <@var{target}> [@var{driver_options ...}]
@end example
@cindex flash bank
@*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
on the flash chip.
@b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
-<@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
-@*CFI flashes require the number of the target they're connected to as an additional
+<@var{target}> [@var{jedec_probe}|@var{x16_as_x8}]
+@*CFI flashes require the name or number of the target they're connected to
+as an additional
argument. The CFI driver makes use of a working area (specified for the target)
to significantly speed up operation.
@subsubsection lpc2000 options
@cindex lpc2000 options
-@b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
+@b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
<@var{clock}> [@var{calc_checksum}]
@*LPC flashes don't require the chip and bus width to be specified. Additional
parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
-or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
-of the target this flash belongs to (first is 0), the frequency at which the core
+or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx),
+the name or number of the target this flash belongs to (first is 0),
+the frequency at which the core
is currently running (in kHz - must be an integral number), and the optional keyword
@var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
vector table.
@subsubsection at91sam7 options
@cindex at91sam7 options
-@b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
-@*AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
+@b{flash bank at91sam7} 0 0 0 0 <@var{target}>
+@*AT91SAM7 flashes only require the @var{target}, all other values are looked up after
reading the chip-id and type.
@subsubsection str7 options
@cindex str7 options
-@b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
+@b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
@*variant can be either STR71x, STR73x or STR75x.
@subsubsection str9 options
@cindex str9 options
-@b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
+@b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target}>
@*The str9 needs the flash controller to be configured prior to Flash programming, e.g.
@example
str9x flash_config 0 4 2 0 0x80000
@subsubsection str9 options (str9xpec driver)
-@b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
+@b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target}>
@*Before using the flash commands the turbo mode must be enabled using str9xpec
@option{enable_turbo} <@var{num>.}
@subsubsection Stellaris (LM3Sxxx) options
@cindex Stellaris (LM3Sxxx) options
-@b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*Stellaris flash plugin only require the @var{target#}.
+@b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target}>
+@*Stellaris flash plugin only require the @var{target}.
@subsubsection stm32x options
@cindex stm32x options
-@b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*stm32x flash plugin only require the @var{target#}.
+@b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target}>
+@*stm32x flash plugin only require the @var{target}.
@subsubsection aduc702x options
@cindex aduc702x options
-@b{flash bank aduc702x} 0 0 0 0 <@var{target#}>
-@*The aduc702x flash plugin works with Analog Devices model numbers ADUC7019 through ADUC7028. The setup command only requires the @var{target#} argument (all devices in this family have the same memory layout).
+@b{flash bank aduc702x} 0 0 0 0 <@var{target}>
+@*The aduc702x flash plugin works with Analog Devices model numbers ADUC7019 through ADUC7028. The setup command only requires the @var{target} argument (all devices in this family have the same memory layout).
-@subsection mFlash configuration
-@cindex mFlash configuration
+@subsection mFlash Configuration
+@cindex mFlash Configuration
@b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
-<@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target #}>
+<@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target}>
@cindex mflash bank
@*Configures a mflash for <@var{soc}> host bank at
<@var{base}>. <@var{chip_width}> and <@var{bus_width}> are bytes
mflash bank pxa270 0x08000000 2 2 43 -1 51 0
@end example
-@section Microcontroller specific flash commands
+@section Microcontroller specific Flash Commands
@subsection AT91SAM7 specific commands
@cindex AT91SAM7 specific commands
@*mass erase flash memory.
@end itemize
-
-@node General commands
-@chapter General commands
+@node NAND Flash Commands
+@chapter NAND Flash Commands
+@cindex NAND
+
+Compared to NOR or SPI flash, NAND devices are inexpensive
+and high density. Today's NAND chips, and multi-chip modules,
+commonly hold multiple GigaBytes of data.
+
+NAND chips consist of a number of ``erase blocks'' of a given
+size (such as 128 KBytes), each of which is divided into a
+number of pages (of perhaps 512 or 2048 bytes each). Each
+page of a NAND flash has an ``out of band'' (OOB) area to hold
+Error Correcting Code (ECC) and other metadata, usually 16 bytes
+of OOB for every 512 bytes of page data.
+
+One key characteristic of NAND flash is that its error rate
+is higher than that of NOR flash. In normal operation, that
+ECC is used to correct and detect errors. However, NAND
+blocks can also wear out and become unusable; those blocks
+are then marked "bad". NAND chips are even shipped from the
+manufacturer with a few bad blocks. The highest density chips
+use a technology (MLC) that wears out more quickly, so ECC
+support is increasingly important as a way to detect blocks
+that have begun to fail, and help to preserve data integrity
+with techniques such as wear leveling.
+
+Software is used to manage the ECC. Some controllers don't
+support ECC directly; in those cases, software ECC is used.
+Other controllers speed up the ECC calculations with hardware.
+Single-bit error correction hardware is routine. Controllers
+geared for newer MLC chips may correct 4 or more errors for
+every 512 bytes of data.
+
+You will need to make sure that any data you write using
+OpenOCD includes the apppropriate kind of ECC. For example,
+that may mean passing the @code{oob_softecc} flag when
+writing NAND data, or ensuring that the correct hardware
+ECC mode is used.
+
+The basic steps for using NAND devices include:
+@enumerate
+@item Declare via the command @command{nand device}
+@* Do this in a board-specific configuration file,
+passing parameters as needed by the controller.
+@item Configure each device using @command{nand probe}.
+@* Do this only after the associated target is set up,
+such as in its reset-init script or in procures defined
+to access that device.
+@item Operate on the flash via @command{nand subcommand}
+@* Often commands to manipulate the flash are typed by a human, or run
+via a script in some automated way. Common task include writing a
+boot loader, operating system, or other data needed to initialize or
+de-brick a board.
+@end enumerate
+
+@section NAND Configuration Commands
+@cindex NAND configuration
+
+NAND chips must be declared in configuration scripts,
+plus some additional configuration that's done after
+OpenOCD has initialized.
+
+@deffn {Config Command} {nand device} controller target [configparams...]
+Declares a NAND device, which can be read and written to
+after it has been configured through @command{nand probe}.
+In OpenOCD, devices are single chips; this is unlike some
+operating systems, which may manage multiple chips as if
+they were a single (larger) device.
+In some cases, configuring a device will activate extra
+commands; see the controller-specific documentation.
+
+@b{NOTE:} This command is not available after OpenOCD
+initialization has completed. Use it in board specific
+configuration files, not interactively.
+
+@itemize @bullet
+@item @var{controller} ... identifies a the controller driver
+associated with the NAND device being declared.
+@xref{NAND Driver List}.
+@item @var{target} ... names the target used when issuing
+commands to the NAND controller.
+@comment Actually, it's currently a controller-specific parameter...
+@item @var{configparams} ... controllers may support, or require,
+additional parameters. See the controller-specific documentation
+for more information.
+@end itemize
+@end deffn
+
+@deffn Command {nand list}
+Prints a one-line summary of each device declared
+using @command{nand device}, numbered from zero.
+Note that un-probed devices show no details.
+@end deffn
+
+@deffn Command {nand probe} num
+Probes the specified device to determine key characteristics
+like its page and block sizes, and how many blocks it has.
+The @var{num} parameter is the value shown by @command{nand list}.
+You must (successfully) probe a device before you can use
+it with most other NAND commands.
+@end deffn
+
+@section Erasing, Reading, Writing to NAND Flash
+
+@deffn Command {nand dump} num filename offset length [oob_option]
+@cindex NAND reading
+Reads binary data from the NAND device and writes it to the file,
+starting at the specified offset.
+The @var{num} parameter is the value shown by @command{nand list}.
+
+Use a complete path name for @var{filename}, so you don't depend
+on the directory used to start the OpenOCD server.
+
+The @var{offset} and @var{length} must be exact multiples of the
+device's page size. They describe a data region; the OOB data
+associated with each such page may also be accessed.
+
+@b{NOTE:} At the time this text was written, no error correction
+was done on the data that's read, unless raw access was disabled
+and the underlying NAND controller driver had a @code{read_page}
+method which handled that error correction.
+
+By default, only page data is saved to the specified file.
+Use an @var{oob_option} parameter to save OOB data:
+@itemize @bullet
+@item no oob_* parameter
+@*Output file holds only page data; OOB is discarded.
+@item @code{oob_raw}
+@*Output file interleaves page data and OOB data;
+the file will be longer than "length" by the size of the
+spare areas associated with each data page.
+Note that this kind of "raw" access is different from
+what's implied by @command{nand raw_access}, which just
+controls whether a hardware-aware access method is used.
+@item @code{oob_only}
+@*Output file has only raw OOB data, and will
+be smaller than "length" since it will contain only the
+spare areas associated with each data page.
+@end itemize
+@end deffn
+
+@deffn Command {nand erase} num ...
+@cindex NAND erasing
+@b{NOTE:} Syntax is in flux.
+@end deffn
+
+@deffn Command {nand write} num filename offset [option...]
+@cindex NAND writing
+Writes binary data from the file into the specified NAND device,
+starting at the specified offset. Those pages should already
+have been erased; you can't change zero bits to one bits.
+The @var{num} parameter is the value shown by @command{nand list}.
+
+Use a complete path name for @var{filename}, so you don't depend
+on the directory used to start the OpenOCD server.
+
+The @var{offset} must be an exact multiple of the device's page size.
+All data in the file will be written, assuming it doesn't run
+past the end of the device.
+Only full pages are written, and any extra space in the last
+page will be filled with 0xff bytes. (That includes OOB data,
+if that's being written.)
+
+@b{NOTE:} At the time this text was written, bad blocks are
+ignored. That is, this routine will not skip bad blocks,
+but will instead try to write them. This can cause problems.
+
+Provide at most one @var{option} parameter. With some
+NAND drivers, the meanings of these parameters may change
+if @command{nand raw_access} was used to disable hardware ECC.
+@itemize @bullet
+@item no oob_* parameter
+@*File has only page data, which is written.
+If raw acccess is in use, the OOB area will not be written.
+Otherwise, if the underlying NAND controller driver has
+a @code{write_page} routine, that routine may write the OOB
+with hardware-computed ECC data.
+@item @code{oob_only}
+@*File has only raw OOB data, which is written to the OOB area.
+Each page's data area stays untouched. @i{This can be a dangerous
+option}, since it can invalidate the ECC data.
+You may need to force raw access to use this mode.
+@item @code{oob_raw}
+@*File interleaves data and OOB data, both of which are written
+If raw access is enabled, the data is written first, then the
+un-altered OOB.
+Otherwise, if the underlying NAND controller driver has
+a @code{write_page} routine, that routine may modify the OOB
+before it's written, to include hardware-computed ECC data.
+@item @code{oob_softecc}
+@*File has only page data, which is written.
+The OOB area is filled with 0xff, except for a standard 1-bit
+software ECC code stored in conventional locations.
+You might need to force raw access to use this mode, to prevent
+the underlying driver from applying hardware ECC.
+@item @code{oob_softecc_kw}
+@*File has only page data, which is written.
+The OOB area is filled with 0xff, except for a 4-bit software ECC
+specific to the boot ROM in Marvell Kirkwood SoCs.
+You might need to force raw access to use this mode, to prevent
+the underlying driver from applying hardware ECC.
+@end itemize
+@end deffn
+
+@section Other NAND commands
+@cindex NAND other commands
+
+@deffn Command {nand check_bad} num ...
+@b{NOTE:} Syntax is in flux.
+@end deffn
+
+@deffn Command {nand info} num
+The @var{num} parameter is the value shown by @command{nand list}.
+This prints the one-line summary from "nand list", plus for
+devices which have been probed this also prints any known
+status for each block.
+@end deffn
+
+@deffn Command {nand raw_access} num <enable|disable>
+Sets or clears an flag affecting how page I/O is done.
+The @var{num} parameter is the value shown by @command{nand list}.
+
+This flag is cleared (disabled) by default, but changing that
+value won't affect all NAND devices. The key factor is whether
+the underlying driver provides @code{read_page} or @code{write_page}
+methods. If it doesn't provide those methods, the setting of
+this flag is irrelevant; all access is effectively ``raw''.
+
+When those methods exist, they are normally used when reading
+data (@command{nand dump} or reading bad block markers) or
+writing it (@command{nand write}). However, enabling
+raw access (setting the flag) prevents use of those methods,
+bypassing hardware ECC logic.
+@i{This can be a dangerous option}, since writing blocks
+with the wrong ECC data can cause them to be marked as bad.
+@end deffn
+
+@section NAND Drivers; Driver-specific Options and Commands
+@anchor{NAND Driver List}
+As noted above, the @command{nand device} command allows
+driver-specific options and behaviors.
+Some controllers also activate controller-specific commands.
+
+@deffn {NAND Driver} lpc3180
+These controllers require an extra @command{nand device}
+parameter: the clock rate used by the controller.
+@deffn Command {nand lpc3180 select} num [mlc|slc]
+Configures use of the MLC or SLC controller mode.
+MLC implies use of hardware ECC.
+The @var{num} parameter is the value shown by @command{nand list}.
+@end deffn
+
+At this writing, this driver includes @code{write_page}
+and @code{read_page} methods. Using @command{nand raw_access}
+to disable those methods will prevent use of hardware ECC
+in the MLC controller mode, but won't change SLC behavior.
+@end deffn
+@comment current lpc3180 code won't issue 5-byte address cycles
+
+@deffn {NAND Driver} orion
+These controllers require an extra @command{nand device}
+parameter: the address of the controller.
+@example
+nand device orion 0xd8000000
+@end example
+These controllers don't define any specialized commands.
+At this writing, their drivers don't include @code{write_page}
+or @code{read_page} methods, so @command{nand raw_access} won't
+change any behavior.
+@end deffn
+
+@deffn {NAND Driver} {s3c2410, s3c2412, s3c2440, s3c2443}
+These S3C24xx family controllers don't have any special
+@command{nand device} options, and don't define any
+specialized commands.
+At this writing, their drivers don't include @code{write_page}
+or @code{read_page} methods, so @command{nand raw_access} won't
+change any behavior.
+@end deffn
+
+@node General Commands
+@chapter General Commands
@cindex commands
The commands documented in this chapter here are common commands that
@subsection fast [@var{enable|disable}]
@cindex fast
-@*Default disabled. Set default behavior of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
+@*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
downloads and fast memory access will work if the JTAG interface isn't too fast and
the core doesn't run at a too low frequency. Note that this option only changes the default
and that the indvidual options, like DCC memory downloads, can be enabled and disabled
individually.
-The target specific "dangerous" optimization tweaking options may come and go
+The target specific "dangerous" optimisation tweaking options may come and go
as more robust and user friendly ways are found to ensure maximum throughput
and robustness with a minimum of configuration.
openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
@end example
+@subsection echo <@var{message}>
+@cindex echo
+@*Output message to stdio. e.g. echo "Programming - please wait"
+
@subsection log_output <@var{file}>
@cindex log_output
@*Redirect logging to <file> (default: stderr)
@*remove watchpoint <adress>
@end itemize
-@section Misc commands
-@cindex Other target commands
+@section Misc Commands
+@cindex Other Target Commands
@itemize
@item @b{profile} <@var{seconds}> <@var{gmon.out}>
@end itemize
-@section Target specific commands
-@cindex Target specific commands
+@section Target Specific Commands
+@cindex Target Specific Commands
@page
-@section Architecture specific commands
-@cindex Architecture specific commands
+@section Architecture Specific Commands
+@cindex Architecture Specific Commands
@subsection ARMV4/5 specific commands
@cindex ARMV4/5 specific commands
@*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
unsafe, especially with targets running at very low speeds. This command was introduced
-with OpenOCD rev. 60.
+with OpenOCD rev. 60, and requires a few bytes of working area.
@end itemize
@subsection ARM720T specific commands
encoding of the [M4:M0] bits of the PSR.
@end itemize
-@section Target requests
-@cindex Target requests
+@section Target Requests
+@cindex Target Requests
OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
See libdcc in the contrib dir for more details.
@itemize @bullet
-@item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
+@item @b{target_request debugmsgs} <@var{enable}|@var{disable}|@var{charmsg}>
@cindex target_request debugmsgs
-@*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
+@*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running. @var{charmsg} receives messages if Linux kernel ``Kernel low-level debugging via EmbeddedICE DCC channel'' option is enabled.
@end itemize
@node JTAG Commands
@chapter TFTP
@cindex TFTP
If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
-be used to access files on PCs (Either the developer's PC or some other PC).
+be used to access files on PCs (either the developer's PC or some other PC).
The way this works on the ZY1000 is to prefix a filename by
"/tftp/ip/" and append the TFTP path on the TFTP
are numerous TFTP servers out there (free and commercial) and you will have to do
a bit of googling to find something that fits your requirements.
-@node Sample scripts
-@chapter Sample scripts
+@node Sample Scripts
+@chapter Sample Scripts
@cindex scripts
-This page shows how to use the target library.
+This page shows how to use the Target Library.
The configuration script can be divided into the following sections:
@itemize @bullet
-@item daemon configuration
-@item interface
-@item jtag scan chain
-@item target configuration
-@item flash configuration
+@item Daemon configuration
+@item Interface
+@item JTAG scan chain
+@item Target configuration
+@item Flash configuration
@end itemize
Detailed information about each section can be found at OpenOCD configuration.
@*OpenOCD can communicate with GDB in two ways:
@enumerate
@item
-A socket (TCP) connection is typically started as follows:
+A socket (TCP/IP) connection is typically started as follows:
@example
target remote localhost:3333
@end example
All other unassigned addresses within GDB are treated as RAM.
GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
-This can be changed to the old behavior by using the following GDB command
+This can be changed to the old behaviour by using the following GDB command
@example
set mem inaccessible-by-default off
@end example
To verify any flash programming the GDB command @option{compare-sections}
can be used.
-@node Tcl scripting API
-@chapter Tcl scripts
-@cindex Tcl scripting API
+@node Tcl Scripting API
+@chapter Tcl Scripting API
+@cindex Tcl Scripting API
@cindex Tcl scripts
@section API rules
startup.tcl "unknown" proc will translate this into a Tcl proc
called "flash_banks".
-@section OpenOCD specific global variables
+@section OpenOCD specific Global Variables
@subsection HostOS
Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
@node Upgrading
-@chapter Deprecated/Removed commands
-@cindex Deprecated/Removed commands
+@chapter Deprecated/Removed Commands
+@cindex Deprecated/Removed Commands
Certain OpenOCD commands have been deprecated/removed during the various revisions.
@itemize @bullet
@item @b{daemon_startup}
@cindex daemon_startup
@*this config option has been removed, simply adding @option{init} and @option{reset halt} to
-the end of your config script will give the same behavior as using @option{daemon_startup reset}
+the end of your config script will give the same behaviour as using @option{daemon_startup reset}
and @option{target cortex_m3 little reset_halt 0}.
@item @b{dump_binary}
@cindex dump_binary
@*use @option{load_image} command with same args. @xref{load_image}.
@item @b{run_and_halt_time}
@cindex run_and_halt_time
-@*This command has been removed for simpler reset behavior, it can be simulated with the
+@*This command has been removed for simpler reset behaviour, it can be simulated with the
following commands:
@smallexample
reset run
@*
In digital circuit design it is often refered to as ``clock
-synchronization'' the JTAG interface uses one clock (TCK or TCLK)
+synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
operating at some speed, your target is operating at another. The two
-clocks are not synchronized, they are ``asynchronous''
+clocks are not synchronised, they are ``asynchronous''
-In order for the two to work together they must be synchronized. Otherwise
+In order for the two to work together they must be synchronised. Otherwise
the two systems will get out of sync with each other and nothing will
work. There are 2 basic options:
@enumerate
The RTCK signal often found in some ARM chips is used to help with
this problem. ARM has a good description of the problem described at
this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
-28/nov/2008]. Link title: ``How does the JTAG synchronization logic
+28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
work? / how does adaptive clocking work?''.
The nice thing about adaptive clocking is that ``battery powered hand
You can use the ``scan_chain'' command to verify and display the tap order.
+Also, some commands can't execute until after @command{init} has been
+processed. Such commands include @command{nand probe} and everything
+else that needs to write to controller registers, perhaps for setting
+up DRAM and loading it with code.
+
@item @b{JTAG Tap Order} JTAG tap order - command order
Many newer devices have multiple JTAG taps. For example: ST
@itemize @bullet
@item @b{[square-brackets]}
-@* @b{[square-brackets]} are command subsitutions. It operates much
+@* @b{[square-brackets]} are command substitutions. It operates much
like Unix Shell `back-ticks`. The result of a [square-bracket]
operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
string}. These two statements are roughly identical:
The consequences of Rule 1 are profound.
-@subsection Tokenization & Execution.
+@subsection Tokenisation & Execution.
Of course, whitespace, blank lines and #comment lines are handled in
the normal way.
As a script is parsed, each (multi) line in the script file is
-tokenized and according to the quoting rules. After tokenization, that
+tokenised and according to the quoting rules. After tokenisation, that
line is immedatly executed.
Multi line statements end with one or more ``still-open''
Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
in the same basic way.
-@section OpenOCD Tcl usage
+@section OpenOCD Tcl Usage
@subsection source and find commands
@b{Where:} In many configuration files
@* Refer to Rule #1.
@item The PUTS command outputs the text.
@end enumerate
-@subsection Body or inlined text
+@subsection Body or Inlined Text
@b{Where:} Various TARGET scripts.
@example
#1 Good
puts [format "X=%d, Y=%d" $x $y]
@}
@end example
-@section Other Tcl hacks
+@section Other Tcl Hacks
@b{Dynamic variable creation}
@example
# Dynamically create a bunch of variables.
@}
@end example
-@node Target library
-@chapter Target library
-@cindex Target library
+@node Target Library
+@chapter Target Library
+@cindex Target Library
OpenOCD comes with a target configuration script library. These scripts can be
used as-is or serve as a starting point.
finally issues the init and reset commands. The communication speed
is set to 10kHz for reset and 8MHz for post reset.
-
@example
openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
@end example
-
To list the target scripts available:
@example
at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
@end example
-
-
@include fdl.texi
-@node OpenOCD Index
+@node OpenOCD Concept Index
@comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
@comment case issue with ``Index.html'' and ``index.html''
@comment Occurs when creating ``--html --no-split'' output
@comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
-@unnumbered OpenOCD Index
+@unnumbered OpenOCD Concept Index
@printindex cp
+@node OpenOCD Command Index
+@unnumbered OpenOCD Command Index
+@printindex fn
+
@bye
Code Review / openocd.git / blobdiff