@menu
* About:: About OpenOCD
* Developers:: OpenOCD Developers
-* Building:: Building OpenOCD
+* Building OpenOCD:: Building OpenOCD From SVN
* JTAG Hardware Dongles:: JTAG Hardware Dongles
* Running:: Running OpenOCD
* Simple Configuration Files:: Simple Configuration Files
@section OpenOCD Subversion Repository
-The ``Building From Source'' section (@xref{Building}) provides
-instructions to retrieve and and build the latest version of the OpenOCD
-source code.
+The ``Building From Source'' section provides instructions to retrieve
+and and build the latest version of the OpenOCD source code.
+@xref{Building OpenOCD}.
Developers that want to contribute patches to the OpenOCD system are
@b{strongly} encouraged to base their work off of the most recent trunk
@uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
-@node Building
+@node Building OpenOCD
@chapter Building OpenOCD
@cindex building
@* Link @url{http://www.hitex.com/stm32-stick}
@item @b{axm0432_jtag}
@* Axiom AXM-0432 Link @url{http://www.axman.com}
+@item @b{cortino}
+@* Link @url{http://www.hitex.com/index.php?id=cortino}
@end itemize
@section USB JLINK based
@example
source [find interface/signalyzer.cfg]
-# Change the default telnet port...
-telnet_port 4444
-# GDB connects here
-gdb_port 3333
# GDB can also flash my flash!
gdb_memory_map enable
gdb_flash_program enable
@node Daemon Configuration
@chapter Daemon Configuration
+@cindex initialization
The commands here are commonly found in the openocd.cfg file and are
used to specify what TCP/IP ports are used, and how GDB should be
supported.
-@section init
-@cindex init
+
+@section Configuration Stage
+@cindex configuration stage
+@cindex configuration command
+
+When the OpenOCD server process starts up, it enters a
+@emph{configuration stage} which is the only time that
+certain commands, @emph{configuration commands}, may be issued.
+Those configuration commands include declaration of TAPs
+and other basic setup.
+The server must leave the configuration stage before it
+may access or activate TAPs.
+After it leaves this stage, configuration commands may no
+longer be issued.
+
+@deffn {Config Command} init
This command terminates the configuration stage and
enters the normal command mode. This can be useful to add commands to
the startup scripts and commands such as resetting the target,
@b{NOTE:} This command normally occurs at or near the end of your
openocd.cfg file to force OpenOCD to ``initialize'' and make the
targets ready. For example: If your openocd.cfg file needs to
-read/write memory on your target - the init command must occur before
+read/write memory on your target, @command{init} must occur before
the memory read/write commands. This includes @command{nand probe}.
+@end deffn
@section TCP/IP Ports
-@itemize @bullet
-@item @b{telnet_port} <@var{number}>
-@cindex telnet_port
-@*Intended for a human. Port on which to listen for incoming telnet connections.
-
-@item @b{tcl_port} <@var{number}>
-@cindex tcl_port
-@*Intended as a machine interface. Port on which to listen for
-incoming Tcl syntax. This port is intended as a simplified RPC
-connection that can be used by clients to issue commands and get the
+@cindex TCP port
+@cindex server
+@cindex port
+The OpenOCD server accepts remote commands in several syntaxes.
+Each syntax uses a different TCP/IP port, which you may specify
+only during configuration (before those ports are opened).
+
+@deffn {Command} gdb_port (number)
+@cindex GDB server
+Specify or query the first port used for incoming GDB connections.
+The GDB port for the
+first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
+When not specified during the configuration stage,
+the port @var{number} defaults to 3333.
+@end deffn
+
+@deffn {Command} tcl_port (number)
+Specify or query the port used for a simplified RPC
+connection that can be used by clients to issue TCL commands and get the
output from the Tcl engine.
+Intended as a machine interface.
+When not specified during the configuration stage,
+the port @var{number} defaults to 6666.
+@end deffn
-@item @b{gdb_port} <@var{number}>
-@cindex gdb_port
-@*First port on which to listen for incoming GDB connections. The GDB port for the
-first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
-@end itemize
+@deffn {Command} telnet_port (number)
+Specify or query the
+port on which to listen for incoming telnet connections.
+This port is intended for interaction with one human through TCL commands.
+When not specified during the configuration stage,
+the port @var{number} defaults to 4444.
+@end deffn
-@section GDB Items
-@itemize @bullet
-@item @b{gdb_breakpoint_override} <@var{hard|soft|disable}>
-@cindex gdb_breakpoint_override
+@section GDB Configuration
+@anchor{GDB Configuration}
+@cindex GDB
+@cindex GDB configuration
+You can reconfigure some GDB behaviors if needed.
+The ones listed here are static and global.
+@xref{Target Create}, about declaring individual targets.
+@xref{Target Events}, about configuring target-specific event handling.
+
+@deffn {Command} gdb_breakpoint_override <hard|soft|disable>
@anchor{gdb_breakpoint_override}
-@*Force breakpoint type for gdb 'break' commands.
-The raison d'etre for this option is to support GDB GUI's without
-a hard/soft breakpoint concept where the default OpenOCD and
-GDB behaviour is not sufficient. Note that GDB will use hardware
+Force breakpoint type for gdb @command{break} commands.
+The raison d'etre for this option is to support GDB GUI's which don't
+distinguish hard versus soft breakpoints, if the default OpenOCD and
+GDB behaviour is not sufficient. GDB normally uses hardware
breakpoints if the memory map has been set up for flash regions.
This option replaces older arm7_9 target commands that addressed
the same issue.
+@end deffn
-@item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
-@cindex gdb_detach
-@*Configures what OpenOCD will do when GDB detaches from the daemon.
-Default behaviour is <@var{resume}>
+@deffn {Config command} gdb_detach <resume|reset|halt|nothing>
+Configures what OpenOCD will do when GDB detaches from the daemon.
+Default behaviour is @var{resume}.
+@end deffn
+
+@deffn {Config command} gdb_flash_program <enable|disable>
+@anchor{gdb_flash_program}
+Set to @var{enable} to cause OpenOCD to program the flash memory when a
+vFlash packet is received.
+The default behaviour is @var{enable}.
+@end deffn
-@item @b{gdb_memory_map} <@var{enable|disable}>
-@cindex gdb_memory_map
-@*Set to <@var{enable}> to cause OpenOCD to send the memory configuration to GDB when
+@deffn {Config command} gdb_memory_map <enable|disable>
+Set to @var{enable} to cause OpenOCD to send the memory configuration to GDB when
requested. GDB will then know when to set hardware breakpoints, and program flash
-using the GDB load command. @option{gdb_flash_program enable} must also be enabled
+using the GDB load command. @command{gdb_flash_program enable} must also be enabled
for flash programming to work.
-Default behaviour is <@var{enable}>
+Default behaviour is @var{enable}.
@xref{gdb_flash_program}.
+@end deffn
-@item @b{gdb_flash_program} <@var{enable|disable}>
-@cindex gdb_flash_program
-@anchor{gdb_flash_program}
-@*Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
-vFlash packet is received.
-Default behaviour is <@var{enable}>
-@comment END GDB Items
-@end itemize
+@deffn {Config command} gdb_report_data_abort <enable|disable>
+Specifies whether data aborts cause an error to be reported
+by GDB memory read packets.
+The default behaviour is @var{disable};
+use @var{enable} see these errors reported.
+@end deffn
@node Interface - Dongle Configuration
@chapter Interface - Dongle Configuration
OOCDLink
@item @b{axm0432_jtag}
Axiom AXM-0432
+@item @b{cortino}
+Hitex Cortino JTAG interface
@end itemize
@item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
Currently, there are no options available for the ep93xx interface.
@section JTAG Speed
-@itemize @bullet
-@item @b{jtag_khz} <@var{reset speed kHz}>
-@cindex jtag_khz
-
-It is debatable if this command belongs here - or in a board
-configuration file. In fact, in some situations the JTAG speed is
-changed during the target initialisation process (i.e.: (1) slow at
-reset, (2) program the CPU clocks, (3) run fast)
-
-Speed 0 (khz) selects RTCK method. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
-
-Not all interfaces support ``rtck''. If the interface device can not
-support the rate asked for, or can not translate from kHz to
-jtag_speed, then an error is returned.
-
-Make sure the JTAG clock is no more than @math{1/6th CPU-Clock}. This is
-especially true for synthesized cores (-S). Also see RTCK.
-
-@b{NOTE: Script writers} If the target chip requires/uses RTCK -
-please use the command: 'jtag_rclk FREQ'. This Tcl proc (in
-startup.tcl) attempts to enable RTCK, if that fails it falls back to
-the specified frequency.
+@anchor{JTAG Speed}
+JTAG clock setup is part of system setup.
+It @emph{does not belong with interface setup} since any interface
+only knows a few of the constraints for the JTAG clock speed.
+Sometimes the JTAG speed is
+changed during the target initialization process: (1) slow at
+reset, (2) program the CPU clocks, (3) run fast.
+Both the "slow" and "fast" clock rates are functions of the
+oscillators used, the chip, the board design, and sometimes
+power management software that may be active.
+
+The speed used during reset can be adjusted using pre_reset
+and post_reset event handlers.
+@xref{Target Events}.
+
+If your system supports adaptive clocking (RTCK), configuring
+JTAG to use that is probably the most robust approach.
+However, it introduces delays to synchronize clocks; so it
+may not be the fastest solution.
+
+@b{NOTE:} Script writers should consider using @command{jtag_rclk}
+instead of @command{jtag_khz}.
+
+@deffn {Command} jtag_khz max_speed_kHz
+A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
+JTAG interfaces usually support a limited number of
+speeds. The speed actually used won't be faster
+than the speed specified.
+
+As a rule of thumb, if you specify a clock rate make
+sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
+This is especially true for synthesized cores (ARMxxx-S).
+
+Speed 0 (khz) selects RTCK method.
+@xref{FAQ RTCK}.
+If your system uses RTCK, you won't need to change the
+JTAG clocking after setup.
+Not all interfaces, boards, or targets support ``rtck''.
+If the interface device can not
+support it, an error is returned when you try to use RTCK.
+@end deffn
+@defun jtag_rclk fallback_speed_kHz
+@cindex RTCK
+This Tcl proc (defined in startup.tcl) attempts to enable RTCK/RCLK.
+If that fails (maybe the interface, board, or target doesn't
+support it), falls back to the specified frequency.
@example
- # Fall back to 3mhz if RCLK is not supported
- jtag_rclk 3000
+# Fall back to 3mhz if RTCK is not supported
+jtag_rclk 3000
@end example
-
-@item @b{DEPRECATED} @b{jtag_speed} - please use jtag_khz above.
-@cindex jtag_speed
-@*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
-speed. The actual effect of this option depends on the JTAG interface used.
-
-The speed used during reset can be adjusted using setting jtag_speed during
-pre_reset and post_reset events.
-@itemize @minus
-
-@item wiggler: maximum speed / @var{number}
-@item ft2232: 6MHz / (@var{number}+1)
-@item amt jtagaccel: 8 / 2**@var{number}
-@item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
-@item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
-@comment end speed list.
-@end itemize
-
-@comment END command list
-@end itemize
+@end defun
@node Reset Configuration
@chapter Reset Configuration
@cindex Reset Configuration
Every system configuration may require a different reset
-configuration. This can also be quite confusing. Please see the
-various board files for example.
-
-@section jtag_nsrst_delay <@var{ms}>
-@cindex jtag_nsrst_delay
-@*How long (in milliseconds) OpenOCD should wait after deasserting
-nSRST before starting new JTAG operations.
-
-@section jtag_ntrst_delay <@var{ms}>
-@cindex jtag_ntrst_delay
-@*Same @b{jtag_nsrst_delay}, but for nTRST
-
-The jtag_n[st]rst_delay options are useful if reset circuitry (like a
-big resistor/capacitor, reset supervisor, or on-chip features). This
-keeps the signal asserted for some time after the external reset got
-deasserted.
-
-@section reset_config
-
-@b{Note:} To maintainers and integrators: Where exactly the
-``reset configuration'' goes is a good question. It touches several
-things at once. In the end, if you have a board file - the board file
-should define it and assume 100% that the DONGLE supports
-anything. However, that does not mean the target should not also make
-not of something the silicon vendor has done inside the
-chip. @i{Grr.... nothing is every pretty.}
-
-@* @b{Problems:}
-@enumerate
-@item Every JTAG Dongle is slightly different, some dongles implement reset differently.
-@item Every board is also slightly different; some boards tie TRST and SRST together.
-@item Every chip is slightly different; some chips internally tie the two signals together.
-@item Some may not implement all of the signals the same way.
-@item Some signals might be push-pull, others open-drain/collector.
-@end enumerate
-@b{Best Case:} OpenOCD can hold the SRST (push-button-reset), then
-reset the TAP via TRST and send commands through the JTAG tap to halt
-the CPU at the reset vector before the 1st instruction is executed,
-and finally release the SRST signal.
-@*Depending on your board vendor, chip vendor, etc., these
-signals may have slightly different names.
-
-OpenOCD defines these signals in these terms:
+configuration. This can also be quite confusing.
+Please see the various board files for examples.
+
+@b{Note} to maintainers and integrators:
+Reset configuration touches several things at once.
+Normally the board configuration file
+should define it and assume that the JTAG adapter supports
+everything that's wired up to the board's JTAG connector.
+However, the target configuration file could also make note
+of something the silicon vendor has done inside the chip,
+which will be true for most (or all) boards using that chip.
+And when the JTAG adapter doesn't support everything, the
+system configuration file will need to override parts of
+the reset configuration provided by other files.
+
+@section Types of Reset
+
+There are many kinds of reset possible through JTAG, but
+they may not all work with a given board and adapter.
+That's part of why reset configuration can be error prone.
+
@itemize @bullet
-@item @b{TRST} - is Tap Reset - and should reset only the TAP.
-@item @b{SRST} - is System Reset - typically equal to a reset push button.
+@item
+@emph{System Reset} ... the @emph{SRST} hardware signal
+resets all chips connected to the JTAG adapter, such as processors,
+power management chips, and I/O controllers. Normally resets triggered
+with this signal behave exactly like pressing a RESET button.
+@item
+@emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
+just the TAP controllers connected to the JTAG adapter.
+Such resets should not be visible to the rest of the system; resetting a
+device's the TAP controller just puts that controller into a known state.
+@item
+@emph{Emulation Reset} ... many devices can be reset through JTAG
+commands. These resets are often distinguishable from system
+resets, either explicitly (a "reset reason" register says so)
+or implicitly (not all parts of the chip get reset).
+@item
+@emph{Other Resets} ... system-on-chip devices often support
+several other types of reset.
+You may need to arrange that a watchdog timer stops
+while debugging, preventing a watchdog reset.
+There may be individual module resets.
@end itemize
-The Command:
+In the best case, OpenOCD can hold SRST, then reset
+the TAPs via TRST and send commands through JTAG to halt the
+CPU at the reset vector before the 1st instruction is executed.
+Then when it finally releases the SRST signal, the system is
+halted under debugger control before any code has executed.
+This is the behavior required to support the @command{reset halt}
+and @command{reset init} commands; after @command{reset init} a
+board-specific script might do things like setting up DRAM.
+(@xref{Reset Command}.)
+
+@section SRST and TRST Signal Issues
+
+Because SRST and TRST are hardware signals, they can have a
+variety of system-specific constraints. Some of the most
+common issues are:
@itemize @bullet
-@item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
-@cindex reset_config
-@* The @t{reset_config} command tells OpenOCD the reset configuration
-of your combination of Dongle, Board, and Chips.
-If the JTAG interface provides SRST, but the target doesn't connect
-that signal properly, then OpenOCD can't use it. <@var{signals}> can
+
+@item @emph{Signal not available} ... Some boards don't wire
+SRST or TRST to the JTAG connector. Some JTAG adapters don't
+support such signals even if they are wired up.
+Use the @command{reset_config} @var{signals} options to say
+when one of those signals is not connected.
+When SRST is not available, your code might not be able to rely
+on controllers having been fully reset during code startup.
+
+@item @emph{Signals shorted} ... Sometimes a chip, board, or
+adapter will connect SRST to TRST, instead of keeping them separate.
+Use the @command{reset_config} @var{combination} options to say
+when those signals aren't properly independent.
+
+@item @emph{Timing} ... Reset circuitry like a resistor/capacitor
+delay circuit, reset supervisor, or on-chip features can extend
+the effect of a JTAG adapter's reset for some time after the adapter
+stops issuing the reset. For example, there may be chip or board
+requirements that all reset pulses last for at least a
+certain amount of time; and reset buttons commonly have
+hardware debouncing.
+Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
+commands to say when extra delays are needed.
+
+@item @emph{Drive type} ... Reset lines often have a pullup
+resistor, letting the JTAG interface treat them as open-drain
+signals. But that's not a requirement, so the adapter may need
+to use push/pull output drivers.
+Also, with weak pullups it may be advisable to drive
+signals to both levels (push/pull) to minimize rise times.
+Use the @command{reset_config} @var{trst_type} and
+@var{srst_type} parameters to say how to drive reset signals.
+@end itemize
+
+There can also be other issues.
+Some devices don't fully conform to the JTAG specifications.
+Others have chip-specific extensions like extra steps needed
+during TAP reset, or a requirement to use the normally-optional TRST
+signal.
+Trivial system-specific differences are common, such as
+SRST and TRST using slightly different names.
+
+@section Commands for Handling Resets
+
+@deffn {Command} jtag_nsrst_delay milliseconds
+How long (in milliseconds) OpenOCD should wait after deasserting
+nSRST (active-low system reset) before starting new JTAG operations.
+When a board has a reset button connected to SRST line it will
+probably have hardware debouncing, implying you should use this.
+@end deffn
+
+@deffn {Command} jtag_ntrst_delay milliseconds
+How long (in milliseconds) OpenOCD should wait after deasserting
+nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
+@end deffn
+
+@deffn {Command} reset_config signals [combination [trst_type [srst_type]]]
+This command tells OpenOCD the reset configuration
+of your combination of JTAG interface, board, and target.
+If the JTAG interface provides SRST, but the board doesn't connect
+that signal properly, then OpenOCD can't use it. @var{signals} can
be @option{none}, @option{trst_only}, @option{srst_only} or
@option{trst_and_srst}.
-[@var{combination}] is an optional value specifying broken reset
+The @var{combination} is an optional value specifying broken reset
signal implementations. @option{srst_pulls_trst} states that the
test logic is reset together with the reset of the system (e.g. Philips
LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
@option{trst_pulls_srst}. The default behaviour if no option given is
@option{separate}.
-The [@var{trst_type}] and [@var{srst_type}] parameters allow the
+The optional @var{trst_type} and @var{srst_type} parameters allow the
driver type of the reset lines to be specified. Possible values are
@option{trst_push_pull} (default) and @option{trst_open_drain} for the
test reset signal, and @option{srst_open_drain} (default) and
@option{srst_push_pull} for the system reset. These values only affect
JTAG interfaces with support for different drivers, like the Amontec
JTAGkey and JTAGAccelerator.
-
-@comment - end command
-@end itemize
-
+@end deffn
@node Tap Creation
@page
@node Target Configuration
@chapter Target Configuration
+@cindex GDB target
This chapter discusses how to create a GDB debug target. Before
creating a ``target'' a JTAG tap DOTTED.NAME must exist first.
@end itemize
@section Target Events
+@cindex events
+@anchor{Target Events}
At various times, certain things can happen, or you want them to happen.
Examples:
@end example
@end itemize
-@section target create
+@section Target Create
+@anchor{Target Create}
@cindex target
@cindex target creation
flash on your board.
@item GDB Flashing
@* Flashing via GDB requires the flash be configured via ``flash
-bank'', and the GDB flash features be enabled. See the daemon
-configuration section for more details.
+bank'', and the GDB flash features be enabled.
+@xref{GDB Configuration}.
@end enumerate
@section Flash commands
de-brick a board.
@end enumerate
+@b{NOTE:} At the time this text was written, the largest NAND
+flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
+This is because the variables used to hold offsets and lengths
+are only 32 bits wide.
+(Larger chips may work in some cases, unless an offset or length
+is larger than 0xffffffff, the largest 32-bit unsigned integer.)
+Some larger devices will work, since they are actually multi-chip
+modules with two smaller chips and individual chipselect lines.
+
@section NAND Configuration Commands
@cindex NAND configuration
@end itemize
@end deffn
-@deffn Command {nand erase} num ...
+@deffn Command {nand erase} num offset length
@cindex NAND erasing
-@b{NOTE:} Syntax is in flux.
+Erases blocks on the specified NAND device, starting at the
+specified @var{offset} and continuing for @var{length} bytes.
+Both of those values must be exact multiples of the device's
+block size, and the region they specify must fit entirely in the chip.
+The @var{num} parameter is the value shown by @command{nand list}.
+
+@b{NOTE:} This command will try to erase bad blocks, when told
+to do so, which will probably invalidate the manufacturer's bad
+block marker.
+For the remainder of the current server session, @command{nand info}
+will still report that the block ``is'' bad.
@end deffn
@deffn Command {nand write} num filename offset [option...]
@section Other NAND commands
@cindex NAND other commands
-@deffn Command {nand check_bad} num ...
-@b{NOTE:} Syntax is in flux.
+@deffn Command {nand check_bad_blocks} [offset length]
+Checks for manufacturer bad block markers on the specified NAND
+device. If no parameters are provided, checks the whole
+device; otherwise, starts at the specified @var{offset} and
+continues for @var{length} bytes.
+Both of those values must be exact multiples of the device's
+block size, and the region they specify must fit entirely in the chip.
+The @var{num} parameter is the value shown by @command{nand list}.
+
+@b{NOTE:} Before using this command you should force raw access
+with @command{nand raw_access enable} to ensure that the underlying
+driver will not try to apply hardware ECC.
@end deffn
@deffn Command {nand info} num
driver-specific options and behaviors.
Some controllers also activate controller-specific commands.
+@deffn {NAND Driver} davinci
+This driver handles the NAND controllers found on DaVinci family
+chips from Texas Instruments.
+It takes three extra parameters:
+address of the NAND chip;
+hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
+address of the AEMIF controller on this processor.
+@example
+nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
+@end example
+All DaVinci processors support the single-bit ECC hardware,
+and newer ones also support the four-bit ECC hardware.
+The @code{write_page} and @code{read_page} methods are used
+to implement those ECC modes, unless they are disabled using
+the @command{nand raw_access} command.
+@end deffn
+
@deffn {NAND Driver} lpc3180
These controllers require an extra @command{nand device}
parameter: the clock rate used by the controller.
or via one of several TCP/IP Ports.
@item @b{From the human}
-@* A human should interact with the telnet interface (default port: 4444,
-or via GDB, default port 3333)
+@* A human should interact with the telnet interface (default port: 4444)
+or via GDB (default port 3333).
To issue commands from within a GDB session, use the @option{monitor}
command, e.g. use @option{monitor poll} to issue the @option{poll}
@cindex step
@*Single-step the target at its current code position, or at an optional address.
+@anchor{Reset Command}
@subsection reset [@option{run}|@option{halt}|@option{init}]
@cindex reset
-@*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
-
-With no arguments a "reset run" is executed
+@*Perform a hard-reset. The optional parameter specifies what should
+happen after the reset.
+If there is no parameter, a @command{reset run} is executed.
+The other options will not work on all systems.
+@xref{Reset Configuration}.
@itemize @minus
@item @b{run}
@cindex reset run
@node GDB and OpenOCD
@chapter GDB and OpenOCD
-@cindex GDB and OpenOCD
+@cindex GDB
OpenOCD complies with the remote gdbserver protocol, and as such can be used
to debug remote targets.
Informing GDB of the memory map of the target will enable GDB to protect any
flash areas of the target and use hardware breakpoints by default. This means
-that the OpenOCD option @option{gdb_breakpoint_override} is not required when
+that the OpenOCD option @command{gdb_breakpoint_override} is not required when
using a memory map. @xref{gdb_breakpoint_override}.
To view the configured memory map in GDB, use the GDB command @option{info mem}
set mem inaccessible-by-default off
@end example
-If @option{gdb_flash_program enable} is also used, GDB will be able to
+If @command{gdb_flash_program enable} is also used, GDB will be able to
program any flash memory using the vFlash interface.
GDB will look at the target memory map when a load command is given, if any
@*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
@item @b{arm7_9 force_hw_bkpts}
@cindex arm7_9 force_hw_bkpts
-@*Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
+@*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
for flash if the GDB memory map has been set up(default when flash is declared in
target configuration). @xref{gdb_breakpoint_override}.
@item @b{arm7_9 sw_bkpts}
@cindex arm7_9 sw_bkpts
-@*On by default. See also @option{gdb_breakpoint_override}. @xref{gdb_breakpoint_override}.
+@*On by default. @xref{gdb_breakpoint_override}.
@item @b{daemon_startup}
@cindex daemon_startup
@*this config option has been removed, simply adding @option{init} and @option{reset halt} to
@item @b{flash auto_erase}
@cindex flash auto_erase
@*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
+
+@item @b{jtag_speed} value
+@*@xref{JTAG Speed}.
+Usually, a value of zero means maximum
+speed. The actual effect of this option depends on the JTAG interface used.
+@itemize @minus
+@item wiggler: maximum speed / @var{number}
+@item ft2232: 6MHz / (@var{number}+1)
+@item amt jtagaccel: 8 / 2**@var{number}
+@item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
+@item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
+@comment end speed list.
+@end itemize
+
@item @b{load_binary}
@cindex load_binary
@*use @option{load_image} command with same args. @xref{load_image}.
@cindex faq
@enumerate
@item @b{RTCK, also known as: Adaptive Clocking - What is it?}
+@anchor{FAQ RTCK}
@cindex RTCK
@cindex adaptive clocking
@*
Code Review / openocd.git / blobdiff