@insertcopying
@menu
-* About:: About OpenOCD.
-* Developers:: OpenOCD developers
-* Building:: Building OpenOCD
+* About:: About OpenOCD
+* Developers:: OpenOCD Developers
+* Building OpenOCD:: Building OpenOCD From SVN
* JTAG Hardware Dongles:: JTAG Hardware Dongles
* Running:: Running OpenOCD
* Simple Configuration Files:: Simple Configuration Files
* Tap Creation:: Tap Creation
* Target Configuration:: Target Configuration
* Flash Configuration:: Flash Configuration
+* NAND Flash Commands:: NAND Flash Commands
* General Commands:: General Commands
* JTAG Commands:: JTAG Commands
* Sample Scripts:: Sample Target Scripts
* TFTP:: TFTP
* GDB and OpenOCD:: Using GDB and OpenOCD
-* TCL scripting API:: Tcl scripting API
+* Tcl Scripting API:: Tcl Scripting API
* Upgrading:: Deprecated/Removed Commands
-* Target library:: Target library
+* Target Library:: Target Library
* FAQ:: Frequently Asked Questions
-* TCL Crash Course:: TCL Crash Course
+* Tcl Crash Course:: Tcl Crash Course
* License:: GNU Free Documentation License
@comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
@comment case issue with ``Index.html'' and ``index.html''
@comment Occurs when creating ``--html --no-split'' output
@comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
-* OpenOCD Index:: Main index.
+* OpenOCD Concept Index:: Concept Index
+* OpenOCD Command Index:: Command Index
@end menu
@node About
@unnumbered About
@cindex about
+OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
+University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
+Since that time, the project has grown into an active open-source project,
+supported by a diverse community of software and hardware developers from
+around the world.
+
+@section What is OpenOCD?
+
The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
in-system programming and boundary-scan testing for embedded target
devices.
@b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
-with the JTAG (IEEE 1149.1) complient taps on your target board.
+with the JTAG (IEEE 1149.1) compliant taps on your target board.
-@b{Dongles:} OpenOCD currently many types of hardware dongles: USB
-Based, Parallel Port Based, and other standalone boxes that run
-OpenOCD internally. See the section titled: @xref{JTAG Hardware Dongles}.
+@b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
+based, parallel port based, and other standalone boxes that run
+OpenOCD internally. @xref{JTAG Hardware Dongles}.
-@b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920t,
-ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
+@b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
+ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be
-debugged via the GDB Protocol.
+debugged via the GDB protocol.
@b{Flash Programing:} Flash writing is supported for external CFI
-compatible flashes (Intel and AMD/Spansion command set) and several
-internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3 and
-STM32x). Preliminary support for using the LPC3180's NAND flash
-controller is included.
+compatible NOR flashes (Intel and AMD/Spansion command set) and several
+internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and
+STM32x). Preliminary support for various NAND flash controllers
+(LPC3180, Orion, S3C24xx, more) controller is included.
+
+@section OpenOCD Web Site
+
+The OpenOCD web site provides the latest public news from the community:
+
+@uref{http://openocd.berlios.de/web/}
+
@node Developers
-@chapter Developers
+@chapter OpenOCD Developer Resources
@cindex developers
-OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
-University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
-Others interested in improving the state of free and open debug and testing technology
-are welcome to participate.
+If you are interested in improving the state of OpenOCD's debugging and
+testing support, new contributions will be welcome. Motivated developers
+can produce new target, flash or interface drivers, improve the
+documentation, as well as more conventional bug fixes and enhancements.
+
+The resources in this chapter are available for developers wishing to explore
+or expand the OpenOCD source code.
-Other developers have contributed support for additional targets and flashes as well
-as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
+@section OpenOCD Subversion Repository
-The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
+The ``Building From Source'' section provides instructions to retrieve
+and and build the latest version of the OpenOCD source code.
+@xref{Building OpenOCD}.
-@node Building
-@chapter Building
-@cindex building OpenOCD
+Developers that want to contribute patches to the OpenOCD system are
+@b{strongly} encouraged to base their work off of the most recent trunk
+revision. Patches created against older versions may require additional
+work from their submitter in order to be updated for newer releases.
+
+@section Doxygen Developer Manual
+
+During the development of the 0.2.0 release, the OpenOCD project began
+providing a Doxygen reference manual. This document contains more
+technical information about the software internals, development
+processes, and similar documentation:
+
+@uref{http://openocd.berlios.de/doc/doxygen/index.html}
+
+This document is a work-in-progress, but contributions would be welcome
+to fill in the gaps. All of the source files are provided in-tree,
+listed in the Doxyfile configuration in the top of the repository trunk.
+
+@section OpenOCD Developer Mailing List
+
+The OpenOCD Developer Mailing List provides the primary means of
+communication between developers:
+
+ @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
+
+All drivers developers are enouraged to also subscribe to the list of
+SVN commits to keep pace with the ongoing changes:
+
+ @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
+
+@node Building OpenOCD
+@chapter Building OpenOCD
+@cindex building
@section Pre-Built Tools
If you are interested in getting actual work done rather than building
you. Chances are that that binary is from some SVN version that is more
stable than SVN trunk where bleeding edge development takes place.
+@section Packagers Please Read!
+
+You are a @b{PACKAGER} of OpenOCD if you
+
+@enumerate
+@item @b{Sell dongles} and include pre-built binaries
+@item @b{Supply tools} i.e.: A complete development solution
+@item @b{Supply IDEs} like Eclipse, or RHIDE, etc.
+@item @b{Build packages} i.e.: RPM files, or DEB files for a Linux Distro
+@end enumerate
+
+As a @b{PACKAGER}, you will experience first reports of most issues.
+When you fix those problems for your users, your solution may help
+prevent hundreds (if not thousands) of other questions from other users.
+
+If something does not work for you, please work to inform the OpenOCD
+developers know how to improve the system or documentation to avoid
+future problems, and follow-up to help us ensure the issue will be fully
+resolved in our future releases.
+
+That said, the OpenOCD developers would also like you to follow a few
+suggestions:
+
+@enumerate
+@item @b{Always build with printer ports enabled.}
+@item @b{Try to use LIBFTDI + LIBUSB where possible. You cover more bases.}
+@end enumerate
+
+@itemize @bullet
+@item @b{Why YES to LIBFTDI + LIBUSB?}
+@itemize @bullet
+@item @b{LESS} work - libusb perhaps already there
+@item @b{LESS} work - identical code, multiple platforms
+@item @b{MORE} dongles are supported
+@item @b{MORE} platforms are supported
+@item @b{MORE} complete solution
+@end itemize
+@item @b{Why not LIBFTDI + LIBUSB} (i.e.: ftd2xx instead)?
+@itemize @bullet
+@item @b{LESS} speed - some say it is slower
+@item @b{LESS} complex to distribute (external dependencies)
+@end itemize
+@end itemize
+
@section Building From Source
-You can download the current SVN version with SVN client of your choice from the
+You can download the current SVN version with an SVN client of your choice from the
following repositories:
- (@uref{svn://svn.berlios.de/openocd/trunk})
+ @uref{svn://svn.berlios.de/openocd/trunk}
or
- (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
+ @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
Using the SVN command line client, you can use the following command to fetch the
latest version (make sure there is no (non-svn) directory called "openocd" in the
svn checkout svn://svn.berlios.de/openocd/trunk openocd
@end example
-Building OpenOCD requires a recent version of the GNU autotools.
-On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
+Building OpenOCD requires a recent version of the GNU autotools (autoconf >= 2.59 and automake >= 1.9).
+For building on Windows,
you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
paths, resulting in obscure dependency errors (This is an observation I've gathered
You further need the appropriate driver files, if you want to build support for
a FTDI FT2232 based interface:
+
@itemize @bullet
@item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
@item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
@item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
-homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
+homepage (@uref{http://www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
@end itemize
-libftdi is supported under windows. Do not use versions earlier then 0.14.
+libftdi is supported under Windows. Do not use versions earlier than 0.14.
In general, the D2XX driver provides superior performance (several times as fast),
but has the draw-back of being binary-only - though that isn't that bad, as it isn't
a kernel module, only a user space library.
To build OpenOCD (on both Linux and Cygwin), use the following commands:
+
@example
./bootstrap
@end example
+
Bootstrap generates the configure script, and prepares building on your system.
+
@example
./configure [options, see below]
@end example
+
Configure generates the Makefiles used to build OpenOCD.
+
@example
make
make install
@end example
+
Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.
The configure script takes several options, specifying which JTAG interfaces
-should be included:
+should be included (among other things):
@itemize @bullet
@item
-@option{--enable-parport} - Bit bang pc printer ports.
+@option{--enable-parport} - Enable building the PC parallel port driver.
+@item
+@option{--enable-parport_ppdev} - Enable use of ppdev (/dev/parportN) for parport.
+@item
+@option{--enable-parport_giveio} - Enable use of giveio for parport instead of ioperm.
+@item
+@option{--enable-amtjtagaccel} - Enable building the Amontec JTAG-Accelerator driver.
@item
-@option{--enable-parport_ppdev} - Parallel Port [see below]
+@option{--enable-ecosboard} - Enable building support for eCosBoard based JTAG debugger.
@item
-@option{--enable-parport_giveio} - Parallel Port [see below]
+@option{--enable-ioutil} - Enable ioutil functions - useful for standalone OpenOCD implementations.
@item
-@option{--enable-amtjtagaccel} - Parallel Port [Amontec, see below]
+@option{--enable-httpd} - Enable builtin httpd server - useful for standalone OpenOCD implementations.
@item
-@option{--enable-ft2232_ftd2xx} - Numerous USB Type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).
+@option{--enable-ep93xx} - Enable building support for EP93xx based SBCs.
@item
-@option{--enable-ft2232_libftdi} - An open source (free) alternate to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin)
+@option{--enable-at91rm9200} - Enable building support for AT91RM9200 based SBCs.
+@item
+@option{--enable-gw16012} - Enable building support for the Gateworks GW16012 JTAG programmer.
+@item
+@option{--enable-ft2232_ftd2xx} - Numerous USB type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).
+@item
+@option{--enable-ft2232_libftdi} - An open source (free) alternative to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin).
@item
@option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c, point at the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
@item
-@option{--with-ftd2xx-linux-tardir=PATH} - Linux only equal of @option{--with-ftd2xx-win32-zipdir}, where you unpacked the TAR.GZ file.
+@option{--with-ftd2xx-linux-tardir=PATH} - Linux only. Equivalent of @option{--with-ftd2xx-win32-zipdir}, where you unpacked the TAR.GZ file.
+@item
+@option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static. Specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. The 'shared' value is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
+@item
+@option{--enable-presto_libftdi} - Enable building support for ASIX Presto programmer using the libftdi driver.
@item
-@option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static, specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. Shared is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
+@option{--enable-presto_ftd2xx} - Enable building support for ASIX Presto programmer using the FTD2XX driver.
@item
-@option{--enable-gw16012}
+@option{--enable-usbprog} - Enable building support for the USBprog JTAG programmer.
@item
-@option{--enable-usbprog}
+@option{--enable-oocd_trace} - Enable building support for the OpenOCD+trace ETM capture device.
@item
-@option{--enable-presto_libftdi}
+@option{--enable-jlink} - Enable building support for the Segger J-Link JTAG programmer.
@item
-@option{--enable-presto_ftd2xx}
+@option{--enable-vsllink} - Enable building support for the Versaloon-Link JTAG programmer.
@item
-@option{--enable-jlink} - From SEGGER
+@option{--enable-rlink} - Enable building support for the Raisonance RLink JTAG programmer.
@item
-@option{--enable-rlink} - Raisonance.com dongle.
+@option{--enable-arm-jtag-ew} - Enable building support for the Olimex ARM-JTAG-EW programmer.
+@item
+@option{--enable-dummy} - Enable building the dummy port driver.
@end itemize
@section Parallel Port Dongles
the @option{--enable-parport_ppdev} option actually is an option to the parport driver
(see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
+The same is true for the @option{--enable-parport_giveio} option, you have to
+use both the @option{--enable-parport} AND the @option{--enable-parport_giveio} option if you want to use giveio instead of ioperm parallel port access method.
+
@section FT2232C Based USB Dongles
There are 2 methods of using the FTD2232, either (1) using the
FTDICHIP.COM closed source driver, or (2) the open (and free) driver
libftdi. Some claim the (closed) FTDICHIP.COM solution is faster.
-The FTDICHIP drivers come as either a (win32) ZIP file, or a (linux)
+The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
TAR.GZ file. You must unpack them ``some where'' convient. As of this
writing (12/26/2008) FTDICHIP does not supply means to install these
files ``in an appropriate place'' As a result, there are two
1) Check out the latest version of ``openocd'' from SVN.
-2) Download & Unpack either the Windows or Linux FTD2xx Drivers
- (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
+2) Download & unpack either the Windows or Linux FTD2xx drivers
+ (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
@example
/home/duane/ftd2xx.win32 => the Cygwin/Win32 ZIP file contents.
- /home/duane/libftd2xx0.4.16 => the Linux TAR file contents.
+ /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents.
@end example
3) Configure with these options:
@example
-Cygwin FTCICHIP solution
- ./configure --prefix=/home/duane/mytools \
- --enable-ft2232_ftd2xx \
- --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
+Cygwin FTDICHIP solution:
+ ./configure --prefix=/home/duane/mytools \
+ --enable-ft2232_ftd2xx \
+ --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
-Linux FTDICHIP solution
+Linux FTDICHIP solution:
./configure --prefix=/home/duane/mytools \
- --enable-ft2232_ftd2xx \
- --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
+ --enable-ft2232_ftd2xx \
+ --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
-Cygwin/Linux LIBFTDI solution
+Cygwin/Linux LIBFTDI solution:
Assumes:
- 1a) For Windows: The windows port of LIBUSB is in place.
- 1b) For Linux: libusb has been built and is inplace.
+ 1a) For Windows: The Windows port of LIBUSB is in place.
+ 1b) For Linux: libusb has been built/installed and is in place.
2) And libftdi has been built and installed
Note: libftdi - relies upon libusb.
./configure --prefix=/home/duane/mytools \
- --enable-ft2232_libftdi
+ --enable-ft2232_libftdi
@end example
4) Then just type ``make'', and perhaps ``make install''.
-@section Miscellaneous configure options
+@section Miscellaneous Configure Options
@itemize @bullet
@item
-@option{--enable-gccwarnings} - enable extra gcc warnings during build
+@option{--disable-option-checking} - Ignore unrecognized @option{--enable} and @option{--with} options.
+@item
+@option{--enable-gccwarnings} - Enable extra gcc warnings during build.
+Default is enabled.
+@item
+@option{--enable-release} - Enable building of an OpenOCD release, generally
+this is for developers. It simply omits the svn version string when the
+openocd @option{-v} is executed.
@end itemize
@node JTAG Hardware Dongles
@chapter JTAG Hardware Dongles
@cindex dongles
-@cindex ftdi
+@cindex FTDI
@cindex wiggler
@cindex zy1000
@cindex printer port
-@cindex usb adapter
+@cindex USB Adapter
@cindex rtck
Defined: @b{dongle}: A small device that plugins into a computer and serves as
In the OpenOCD case, this generally refers to @b{a small adapater} one
attaches to your computer via USB or the Parallel Printer Port. The
execption being the Zylin ZY1000 which is a small box you attach via
-an ethernet cable.
+an ethernet cable. The Zylin ZY1000 has the advantage that it does not
+require any drivers to be installed on the developer PC. It also has
+a built in web interface. It supports RTCK/RCLK or adaptive clocking
+and has a built in relay to power cycle targets remotely.
@section Choosing a Dongle
@section Stand alone Systems
@b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
-dongle, but a standalone box.
+dongle, but a standalone box. The ZY1000 has the advantage that it does
+not require any drivers installed on the developer PC. It also has
+a built in web interface. It supports RTCK/RCLK or adaptive clocking
+and has a built in relay to power cycle targets remotely.
@section USB FT2232 Based
-There are many USB jtag dongles on the market, many of them are based
+There are many USB JTAG dongles on the market, many of them are based
on a chip from ``Future Technology Devices International'' (FTDI)
known as the FTDI FT2232.
@* Link @url{http://www.hitex.com/stm32-stick}
@item @b{axm0432_jtag}
@* Axiom AXM-0432 Link @url{http://www.axman.com}
+@item @b{cortino}
+@* Link @url{http://www.hitex.com/index.php?id=cortino}
@end itemize
@section USB JLINK based
@item @b{USB - Presto}
@* Link: @url{http://tools.asix.net/prg_presto.htm}
+
+@item @b{Versaloon-Link}
+@* Link: @url{http://www.simonqian.com/en/Versaloon}
+
+@item @b{ARM-JTAG-EW}
+@* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
@end itemize
@section IBM PC Parallel Printer Port Based
@itemize @bullet
@item @b{ep93xx}
-@* An EP93xx based linux machine using the GPIO pins directly.
+@* An EP93xx based Linux machine using the GPIO pins directly.
@item @b{at91rm9200}
@* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
target library is in the search path by default.
For details on the @option{-p} option. @xref{Connecting to GDB}.
-Option @option{-p} is not currently supported under native win32.
Note! OpenOCD will launch the GDB & telnet server even if it can not
establish a connection with the target. In general, it is possible for
@section Small configuration file method
-This is the prefered method, it is simple and is works well for many
-people. The developers of OpenOCD would encourage you to use this
+This is the preferred method. It is simple and works well for many
+people. The developers of OpenOCD would encourage you to use this
method. If you create a new configuration please email new
configurations to the development list.
@example
source [find interface/signalyzer.cfg]
-# Change the default telnet port...
-telnet_port 4444
-# GDB connects here
-gdb_port 3333
# GDB can also flash my flash!
gdb_memory_map enable
gdb_flash_program enable
Some key things you should look at and understand are:
@enumerate
-@item The RESET configuration of your debug environment as a hole
+@item The reset configuration of your debug environment as a whole
@item Is there a ``work area'' that OpenOCD can use?
@* For ARM - work areas mean up to 10x faster downloads.
-@item For MMU/MPU based ARM chips (ie: ARM9 and later) will that work area still be available?
+@item For MMU/MPU based ARM chips (i.e.: ARM9 and later) will that work area still be available?
@item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
@end enumerate
OpenOCD. These are guidelines for creating new boards and new target
configurations as of 28/Nov/2008.
-However, you the user of OpenOCD should be some what familiar with
+However, you, the user of OpenOCD, should be somewhat familiar with
this section as it should help explain some of the internals of what
you might be looking at.
-The user should find under @t{$(INSTALLDIR)/lib/openocd} the
-following directories:
+The user should find the following directories under @t{$(INSTALLDIR)/lib/openocd} :
@itemize @bullet
@item @b{interface}
-@*Think JTAG Dongle. Files that configure the jtag dongle go here.
+@*Think JTAG Dongle. Files that configure the JTAG dongle go here.
@item @b{board}
-@* Thing Circuit Board, PWA, PCB, they go by many names. Board files
+@* Think Circuit Board, PWA, PCB, they go by many names. Board files
contain initialization items that are specific to a board - for
example: The SDRAM initialization sequence for the board, or the type
of external flash and what address it is found at. Any initialization
-sequence to enable that external flash or sdram should be found in the
-board file. Boards may also contain multiple targets, ie: Two cpus, or
+sequence to enable that external flash or SDRAM should be found in the
+board file. Boards may also contain multiple targets, i.e.: Two CPUs, or
a CPU and an FPGA or CPLD.
@item @b{target}
-@* Think CHIP. The ``target'' directory represents a jtag tap (or
+@* Think chip. The ``target'' directory represents a JTAG tap (or
chip) OpenOCD should control, not a board. Two common types of targets
are ARM chips and FPGA or CPLD chips.
@end itemize
today, that said, perhaps some interfaces have only been used by the
sole developer who created it.
-@b{FIXME/NOTE:} We need to add support for a variable like TCL variable
+@b{FIXME/NOTE:} We need to add support for a variable like Tcl variable
tcl_platform(platform), it should be called jim_platform (because it
is jim, not real tcl) and it should contain 1 of 3 words: ``linux'',
``cygwin'' or ``mingw''
The board file should contain one or more @t{source [find
target/FOO.cfg]} statements along with any board specific things.
-In summery the board files should contain (if present)
+In summary the board files should contain (if present)
@enumerate
-@item External flash configuration (ie: the flash on CS0)
-@item SDRAM configuration (size, speed, etc)
-@item Board specific IO configuration (ie: GPIO pins might disable a 2nd flash)
+@item External flash configuration (i.e.: NOR flash on CS0, two NANDs on CS2)
+@item SDRAM configuration (size, speed, etc.
+@item Board specific IO configuration (i.e.: GPIO pins might disable a 2nd flash)
@item Multiple TARGET source statements
@item All things that are not ``inside a chip''
@item Things inside a chip go in a 'target' file
openocd -f target/FOOBAR.cfg
@end example
-In summery the target files should contain
+In summary the target files should contain
@enumerate
-@item Set Defaults
-@item Create Taps
-@item Reset Configuration
-@item Work Areas
-@item CPU/Chip/CPU-Core Specific features
-@item OnChip Flash
+@item Set defaults
+@item Create taps
+@item Reset configuration
+@item Work areas
+@item CPU/Chip/CPU-Core specific features
+@item On-Chip flash
@end enumerate
@subsection Important variable names
@* When OpenOCD examines the JTAG chain, it will attempt to identify
every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
to verify the tap id number verses configuration file and may issue an
-error or warning like this. The hope is this will help pin point
-problem OpenOCD configurations.
+error or warning like this. The hope is that this will help to pinpoint
+problems in OpenOCD configurations.
@example
Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
At no time should the name ``target0'' (the default target name if
none was specified) be used. The name ``target0'' is a hard coded name
- the next target on the board will be some other number.
+In the same way, avoid using target numbers even when they are
+permitted; use the right target name(s) for your board.
The user (or board file) should reasonably be able to:
@end itemize
-@subsection TCL Variables Guide Line
+@subsection Tcl Variables Guide Line
The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
Thus the rule we follow in OpenOCD is this: Variables that begin with
-a leading underscore are temporal in nature, and can be modified and
-used at will within a ?TARGET? configuration file
+a leading underscore are temporary in nature, and can be modified and
+used at will within a ?TARGET? configuration file.
@b{EXAMPLE:} The user should be able to do this:
source [find target/pxa270.cfg]
# variable: _TARGETNAME = network.cpu
# other commands can refer to the "network.cpu" tap.
- $_TARGETNAME configure .... params for this cpu..
+ $_TARGETNAME configure .... params for this CPU..
set ENDIAN little
set CHIPNAME video
source [find target/pxa270.cfg]
# variable: _TARGETNAME = video.cpu
# other commands can refer to the "video.cpu" tap.
- $_TARGETNAME configure .... params for this cpu..
+ $_TARGETNAME configure .... params for this CPU..
unset ENDIAN
set CHIPNAME xilinx
@end example
@subsection Creating Taps
-After the ``defaults'' are choosen, [see above], the taps are created.
+After the ``defaults'' are choosen [see above] the taps are created.
@b{SIMPLE example:} such as an Atmel AT91SAM7X256
@b{Tap Naming Convention}
-See the command ``jtag newtap'' for detail, but in breif the names you should use are:
+See the command ``jtag newtap'' for detail, but in brief the names you should use are:
@itemize @bullet
@item @b{tap}
@item @b{cpu}
@item @b{flash}
@item @b{bs}
+@item @b{etb}
@item @b{jrc}
@item @b{unknownN} - it happens :-(
@end itemize
@subsection Work Areas
Work areas are small RAM areas used by OpenOCD to speed up downloads,
-and to download small snippits of code to program flash chips.
+and to download small snippets of code to program flash chips.
-If the chip includes an form of ``on-chip-ram'' - and many do - define
+If the chip includes a form of ``on-chip-ram'' - and many do - define
a reasonable work area and use the ``backup'' option.
@b{PROBLEMS:} On more complex chips, this ``work area'' may become
-inaccessable if/when the application code enables or disables the MMU.
+inaccessible if/when the application code enables or disables the MMU.
@subsection ARM Core Specific Hacks
-If the chip has a DCC, enable it. If the chip is an arm9 with some
-special high speed download - enable it.
+If the chip has a DCC, enable it. If the chip is an ARM9 with some
+special high speed download features - enable it.
-If the chip has an ARM ``vector catch'' feature - by defeault enable
+If the chip has an ARM ``vector catch'' feature - by default enable
it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
user is really writing a handler for those situations - they can
easily disable it. Experiance has shown the ``vector catch'' is
If present, the MMU, the MPU and the CACHE should be disabled.
+Some ARM cores are equipped with trace support, which permits
+examination of the instruction and data bus activity. Trace
+activity is controlled through an ``Embedded Trace Module'' (ETM)
+on one of the core's scan chains. The ETM emits voluminous data
+through a ``trace port''. The trace port is accessed in one
+of two ways. When its signals are pinned out from the chip,
+boards may provide a special high speed debugging connector;
+software support for this is not configured by default, use
+the ``--enable-oocd_trace'' option. Alternatively, trace data
+may be stored an on-chip SRAM which is packaged as an ``Embedded
+Trace Buffer'' (ETB). An ETB has its own TAP, usually right after
+its associated ARM core. OpenOCD supports the ETM, and your
+target configuration should set it up with the relevant trace
+port: ``etb'' for chips which use that, else the board-specific
+option will be either ``oocd_trace'' or ``dummy''.
+
+@example
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
+@end example
+
@subsection Internal Flash Configuration
This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
@b{Never ever} in the ``target configuration file'' define any type of
-flash that is external to the chip. (For example the BOOT flash on
-Chip Select 0). The BOOT flash information goes in a board file - not
+flash that is external to the chip. (For example a BOOT flash on
+Chip Select 0.) Such flash information goes in a board file - not
the TARGET (chip) file.
Examples:
learn more about JIM here: @url{http://jim.berlios.de}
@itemize @bullet
-@item @b{JIM vrs TCL}
+@item @b{JIM vs. Tcl}
@* JIM-TCL is a stripped down version of the well known Tcl language,
which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
fewer features. JIM-Tcl is a single .C file and a single .H file and
-impliments the basic TCL command set along. In contrast: Tcl 8.6 is a
-4.2MEG zip file containing 1540 files.
+impliments the basic Tcl command set along. In contrast: Tcl 8.6 is a
+4.2 MB .zip file containing 1540 files.
@item @b{Missing Features}
-@* Our practice has been: Add/clone the Real TCL feature if/when
+@* Our practice has been: Add/clone the real Tcl feature if/when
needed. We welcome JIM Tcl improvements, not bloat.
@item @b{Scripts}
@* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
-command interpretor today (28/nov/2008) is a mixture of (newer)
-JIM-Tcl commands, and (older) the orginal command interpretor.
+command interpreter today (28/nov/2008) is a mixture of (newer)
+JIM-Tcl commands, and (older) the orginal command interpreter.
@item @b{Commands}
@* At the OpenOCD telnet command line (or via the GDB mon command) one
can type a Tcl for() loop, set variables, etc.
@item @b{Historical Note}
-@* JIM-Tcl was introduced to OpenOCD in Spring 2008.
+@* JIM-Tcl was introduced to OpenOCD in spring 2008.
-@item @b{Need a Crash Course In TCL?}
-@* See: @xref{TCL Crash Course}.
+@item @b{Need a crash course in Tcl?}
+@* See: @xref{Tcl Crash Course}.
@end itemize
@node Daemon Configuration
@chapter Daemon Configuration
+@cindex initialization
The commands here are commonly found in the openocd.cfg file and are
used to specify what TCP/IP ports are used, and how GDB should be
supported.
-@section init
-@cindex init
+
+@section Configuration Stage
+@cindex configuration stage
+@cindex configuration command
+
+When the OpenOCD server process starts up, it enters a
+@emph{configuration stage} which is the only time that
+certain commands, @emph{configuration commands}, may be issued.
+Those configuration commands include declaration of TAPs
+and other basic setup.
+The server must leave the configuration stage before it
+may access or activate TAPs.
+After it leaves this stage, configuration commands may no
+longer be issued.
+
+@deffn {Config Command} init
This command terminates the configuration stage and
enters the normal command mode. This can be useful to add commands to
the startup scripts and commands such as resetting the target,
@b{NOTE:} This command normally occurs at or near the end of your
openocd.cfg file to force OpenOCD to ``initialize'' and make the
targets ready. For example: If your openocd.cfg file needs to
-read/write memory on your target - the init command must occur before
-the memory read/write commands.
+read/write memory on your target, @command{init} must occur before
+the memory read/write commands. This includes @command{nand probe}.
+@end deffn
@section TCP/IP Ports
-@itemize @bullet
-@item @b{telnet_port} <@var{number}>
-@cindex telnet_port
-@*Intended for a human. Port on which to listen for incoming telnet connections.
-
-@item @b{tcl_port} <@var{number}>
-@cindex tcl_port
-@*Intended as a machine interface. Port on which to listen for
-incoming TCL syntax. This port is intended as a simplified RPC
-connection that can be used by clients to issue commands and get the
-output from the TCL engine.
-
-@item @b{gdb_port} <@var{number}>
-@cindex gdb_port
-@*First port on which to listen for incoming GDB connections. The GDB port for the
-first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
-@end itemize
-
-@section GDB Items
-@itemize @bullet
-@item @b{gdb_breakpoint_override} <@var{hard|soft|disabled}>
-@cindex gdb_breakpoint_override
+@cindex TCP port
+@cindex server
+@cindex port
+The OpenOCD server accepts remote commands in several syntaxes.
+Each syntax uses a different TCP/IP port, which you may specify
+only during configuration (before those ports are opened).
+
+@deffn {Command} gdb_port (number)
+@cindex GDB server
+Specify or query the first port used for incoming GDB connections.
+The GDB port for the
+first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
+When not specified during the configuration stage,
+the port @var{number} defaults to 3333.
+@end deffn
+
+@deffn {Command} tcl_port (number)
+Specify or query the port used for a simplified RPC
+connection that can be used by clients to issue TCL commands and get the
+output from the Tcl engine.
+Intended as a machine interface.
+When not specified during the configuration stage,
+the port @var{number} defaults to 6666.
+@end deffn
+
+@deffn {Command} telnet_port (number)
+Specify or query the
+port on which to listen for incoming telnet connections.
+This port is intended for interaction with one human through TCL commands.
+When not specified during the configuration stage,
+the port @var{number} defaults to 4444.
+@end deffn
+
+@section GDB Configuration
+@anchor{GDB Configuration}
+@cindex GDB
+@cindex GDB configuration
+You can reconfigure some GDB behaviors if needed.
+The ones listed here are static and global.
+@xref{Target Create}, about declaring individual targets.
+@xref{Target Events}, about configuring target-specific event handling.
+
+@deffn {Command} gdb_breakpoint_override <hard|soft|disable>
@anchor{gdb_breakpoint_override}
-@*Force breakpoint type for gdb 'break' commands.
-The raison d'etre for this option is to support GDB GUI's without
-a hard/soft breakpoint concept where the default OpenOCD and
-GDB behaviour is not sufficient. Note that GDB will use hardware
+Force breakpoint type for gdb @command{break} commands.
+The raison d'etre for this option is to support GDB GUI's which don't
+distinguish hard versus soft breakpoints, if the default OpenOCD and
+GDB behaviour is not sufficient. GDB normally uses hardware
breakpoints if the memory map has been set up for flash regions.
This option replaces older arm7_9 target commands that addressed
the same issue.
+@end deffn
+
+@deffn {Config command} gdb_detach <resume|reset|halt|nothing>
+Configures what OpenOCD will do when GDB detaches from the daemon.
+Default behaviour is @var{resume}.
+@end deffn
-@item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
-@cindex gdb_detach
-@*Configures what OpenOCD will do when gdb detaches from the daeman.
-Default behaviour is <@var{resume}>
+@deffn {Config command} gdb_flash_program <enable|disable>
+@anchor{gdb_flash_program}
+Set to @var{enable} to cause OpenOCD to program the flash memory when a
+vFlash packet is received.
+The default behaviour is @var{enable}.
+@end deffn
-@item @b{gdb_memory_map} <@var{enable|disable}>
-@cindex gdb_memory_map
-@*Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
-requested. gdb will then know when to set hardware breakpoints, and program flash
-using the gdb load command. @option{gdb_flash_program enable} will also need enabling
+@deffn {Config command} gdb_memory_map <enable|disable>
+Set to @var{enable} to cause OpenOCD to send the memory configuration to GDB when
+requested. GDB will then know when to set hardware breakpoints, and program flash
+using the GDB load command. @command{gdb_flash_program enable} must also be enabled
for flash programming to work.
-Default behaviour is <@var{enable}>
+Default behaviour is @var{enable}.
@xref{gdb_flash_program}.
+@end deffn
-@item @b{gdb_flash_program} <@var{enable|disable}>
-@cindex gdb_flash_program
-@anchor{gdb_flash_program}
-@*Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
-vFlash packet is received.
-Default behaviour is <@var{enable}>
-@comment END GDB Items
-@end itemize
+@deffn {Config command} gdb_report_data_abort <enable|disable>
+Specifies whether data aborts cause an error to be reported
+by GDB memory read packets.
+The default behaviour is @var{disable};
+use @var{enable} see these errors reported.
+@end deffn
@node Interface - Dongle Configuration
@chapter Interface - Dongle Configuration
parport_cable wiggler
jtag_speed 0
@end verbatim
-@section Interface Conmmand
+@b{ARM-JTAG-EW}
+@verbatim
+interface arm-jtag-ew
+@end verbatim
+@section Interface Command
-The interface command tells OpenOCD what type of jtag dongle you are
-using. Depending upon the type of dongle, you may need to have one or
+The interface command tells OpenOCD what type of JTAG dongle you are
+using. Depending on the type of dongle, you may need to have one or
more additional commands.
@itemize @bullet
@* Gateworks GW16012 JTAG programmer.
@item @b{jlink}
-@* Segger jlink usb adapter
+@* Segger jlink USB adapter
@item @b{rlink}
-@* Raisonance RLink usb adapter
+@* Raisonance RLink USB adapter
+
+@item @b{vsllink}
+@* vsllink is part of Versaloon which is a versatile USB programmer.
+
+@item @b{arm-jtag-ew}
+@* Olimex ARM-JTAG-EW USB adapter
@comment - End parameters
@end itemize
@comment - End Interface
specified, the FTDI default value is used. This setting is only valid
if compiled with FTD2XX support.
-@b{TODO:} Confirm the following: On windows the name needs to end with
+@b{TODO:} Confirm the following: On Windows the name needs to end with
a ``space A''? Or not? It has to do with the FTD2xx driver. When must
this be added and when must it not be added? Why can't the code in the
interface or in OpenOCD automatically add this if needed? -- Duane.
@item @b{usbjtag}
"USBJTAG-1" layout described in the original OpenOCD diploma thesis
@item @b{jtagkey}
-Amontec JTAGkey and JTAGkey-tiny
+Amontec JTAGkey and JTAGkey-Tiny
@item @b{signalyzer}
Signalyzer
@item @b{olimex-jtag}
OOCDLink
@item @b{axm0432_jtag}
Axiom AXM-0432
+@item @b{cortino}
+Hitex Cortino JTAG interface
@end itemize
@item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
@*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
-default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
+default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, e.g.
@example
ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
@end example
@item @b{ft2232_latency} <@var{ms}>
-@*On some systems using ft2232 based JTAG interfaces the FT_Read function call in
+@*On some systems using FT2232 based JTAG interfaces the FT_Read function call in
ft2232_read() fails to return the expected number of bytes. This can be caused by
USB communication delays and has proved hard to reproduce and debug. Setting the
-FT2232 latency timer to a larger value increases delays for short USB packages but it
+FT2232 latency timer to a larger value increases delays for short USB packets but it
also reduces the risk of timeouts before receiving the expected number of bytes.
-The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
+The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
@end itemize
@subsection ep93xx options
Currently, there are no options available for the ep93xx interface.
@section JTAG Speed
-@itemize @bullet
-@item @b{jtag_khz} <@var{reset speed kHz}>
-@cindex jtag_khz
-
-It is debatable if this command belongs here - or in a board
-configuration file. In fact, in some situations the jtag speed is
-changed during the target initialization process (ie: (1) slow at
-reset, (2) program the cpu clocks, (3) run fast)
-
-Speed 0 (khz) selects RTCK method. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
-
-Not all interfaces support ``rtck''. If the interface device can not
-support the rate asked for, or can not translate from kHz to
-jtag_speed, then an error is returned.
-
-Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
-especially true for synthesized cores (-S). Also see RTCK.
-
-@b{NOTE: Script writers} If the target chip requires/uses RTCK -
-please use the command: 'jtag_rclk FREQ'. This TCL proc (in
-startup.tcl) attempts to enable RTCK, if that fails it falls back to
-the specified frequency.
-
+@anchor{JTAG Speed}
+JTAG clock setup is part of system setup.
+It @emph{does not belong with interface setup} since any interface
+only knows a few of the constraints for the JTAG clock speed.
+Sometimes the JTAG speed is
+changed during the target initialization process: (1) slow at
+reset, (2) program the CPU clocks, (3) run fast.
+Both the "slow" and "fast" clock rates are functions of the
+oscillators used, the chip, the board design, and sometimes
+power management software that may be active.
+
+The speed used during reset can be adjusted using pre_reset
+and post_reset event handlers.
+@xref{Target Events}.
+
+If your system supports adaptive clocking (RTCK), configuring
+JTAG to use that is probably the most robust approach.
+However, it introduces delays to synchronize clocks; so it
+may not be the fastest solution.
+
+@b{NOTE:} Script writers should consider using @command{jtag_rclk}
+instead of @command{jtag_khz}.
+
+@deffn {Command} jtag_khz max_speed_kHz
+A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
+JTAG interfaces usually support a limited number of
+speeds. The speed actually used won't be faster
+than the speed specified.
+
+As a rule of thumb, if you specify a clock rate make
+sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
+This is especially true for synthesized cores (ARMxxx-S).
+
+Speed 0 (khz) selects RTCK method.
+@xref{FAQ RTCK}.
+If your system uses RTCK, you won't need to change the
+JTAG clocking after setup.
+Not all interfaces, boards, or targets support ``rtck''.
+If the interface device can not
+support it, an error is returned when you try to use RTCK.
+@end deffn
+
+@defun jtag_rclk fallback_speed_kHz
+@cindex RTCK
+This Tcl proc (defined in startup.tcl) attempts to enable RTCK/RCLK.
+If that fails (maybe the interface, board, or target doesn't
+support it), falls back to the specified frequency.
@example
- # Fall back to 3mhz if RCLK is not supported
- jtag_rclk 3000
+# Fall back to 3mhz if RTCK is not supported
+jtag_rclk 3000
@end example
-
-@item @b{DEPRICATED} @b{jtag_speed} - please use jtag_khz above.
-@cindex jtag_speed
-@*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
-speed. The actual effect of this option depends on the JTAG interface used.
-
-The speed used during reset can be adjusted using setting jtag_speed during
-pre_reset and post_reset events.
-@itemize @minus
-
-@item wiggler: maximum speed / @var{number}
-@item ft2232: 6MHz / (@var{number}+1)
-@item amt jtagaccel: 8 / 2**@var{number}
-@item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
-@item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
-@comment end speed list.
-@end itemize
-
-@comment END command list
-@end itemize
+@end defun
@node Reset Configuration
@chapter Reset Configuration
-@cindex reset configuration
+@cindex Reset Configuration
Every system configuration may require a different reset
-configuration. This can also be quite confusing. Please see the
-various board files for example.
-
-@section jtag_nsrst_delay <@var{ms}>
-@cindex jtag_nsrst_delay
-@*How long (in milliseconds) OpenOCD should wait after deasserting
-nSRST before starting new JTAG operations.
-
-@section jtag_ntrst_delay <@var{ms}>
-@cindex jtag_ntrst_delay
-@*Same @b{jtag_nsrst_delay}, but for nTRST
-
-The jtag_n[st]rst_delay options are useful if reset circuitry (like a
-big resistor/capacitor, reset supervisor, or on-chip features). This
-keeps the signal asserted for some time after the external reset got
-deasserted.
-
-@section reset_config
-
-@b{Note:} To maintainer types and integrators. Where exactly the
-``reset configuration'' goes is a good question. It touches several
-things at once. In the end, if you have a board file - the board file
-should define it and assume 100% that the DONGLE supports
-anything. However, that does not mean the target should not also make
-not of something the silicon vendor has done inside the
-chip. @i{Grr.... nothing is every pretty.}
-
-@* @b{Problems:}
-@enumerate
-@item Every JTAG Dongle is slightly different, some dongles impliment reset differently.
-@item Every board is also slightly different; some boards tie TRST and SRST together.
-@item Every chip is slightly different; some chips internally tie the two signals together.
-@item Some may not impliment all of the signals the same way.
-@item Some signals might be push-pull, others open-drain/collector.
-@end enumerate
-@b{Best Case:} OpenOCD can hold the SRST (push-button-reset), then
-reset the TAP via TRST and send commands through the JTAG tap to halt
-the CPU at the reset vector before the 1st instruction is executed,
-and finally release the SRST signal.
-@*Depending upon your board vendor, your chip vendor, etc, these
-signals may have slightly different names.
+configuration. This can also be quite confusing.
+Please see the various board files for examples.
+
+@b{Note} to maintainers and integrators:
+Reset configuration touches several things at once.
+Normally the board configuration file
+should define it and assume that the JTAG adapter supports
+everything that's wired up to the board's JTAG connector.
+However, the target configuration file could also make note
+of something the silicon vendor has done inside the chip,
+which will be true for most (or all) boards using that chip.
+And when the JTAG adapter doesn't support everything, the
+system configuration file will need to override parts of
+the reset configuration provided by other files.
+
+@section Types of Reset
+
+There are many kinds of reset possible through JTAG, but
+they may not all work with a given board and adapter.
+That's part of why reset configuration can be error prone.
-OpenOCD defines these signals in these terms:
@itemize @bullet
-@item @b{TRST} - is Tap Reset - and should reset only the TAP.
-@item @b{SRST} - is System Reset - typically equal to a reset push button.
+@item
+@emph{System Reset} ... the @emph{SRST} hardware signal
+resets all chips connected to the JTAG adapter, such as processors,
+power management chips, and I/O controllers. Normally resets triggered
+with this signal behave exactly like pressing a RESET button.
+@item
+@emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
+just the TAP controllers connected to the JTAG adapter.
+Such resets should not be visible to the rest of the system; resetting a
+device's the TAP controller just puts that controller into a known state.
+@item
+@emph{Emulation Reset} ... many devices can be reset through JTAG
+commands. These resets are often distinguishable from system
+resets, either explicitly (a "reset reason" register says so)
+or implicitly (not all parts of the chip get reset).
+@item
+@emph{Other Resets} ... system-on-chip devices often support
+several other types of reset.
+You may need to arrange that a watchdog timer stops
+while debugging, preventing a watchdog reset.
+There may be individual module resets.
@end itemize
-The Command:
+In the best case, OpenOCD can hold SRST, then reset
+the TAPs via TRST and send commands through JTAG to halt the
+CPU at the reset vector before the 1st instruction is executed.
+Then when it finally releases the SRST signal, the system is
+halted under debugger control before any code has executed.
+This is the behavior required to support the @command{reset halt}
+and @command{reset init} commands; after @command{reset init} a
+board-specific script might do things like setting up DRAM.
+(@xref{Reset Command}.)
+
+@section SRST and TRST Signal Issues
+
+Because SRST and TRST are hardware signals, they can have a
+variety of system-specific constraints. Some of the most
+common issues are:
@itemize @bullet
-@item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
-@cindex reset_config
-@* The @t{reset_config} command tells OpenOCD the reset configuration
-of your combination of Dongle, Board, and Chips.
-If the JTAG interface provides SRST, but the target doesn't connect
-that signal properly, then OpenOCD can't use it. <@var{signals}> can
+
+@item @emph{Signal not available} ... Some boards don't wire
+SRST or TRST to the JTAG connector. Some JTAG adapters don't
+support such signals even if they are wired up.
+Use the @command{reset_config} @var{signals} options to say
+when one of those signals is not connected.
+When SRST is not available, your code might not be able to rely
+on controllers having been fully reset during code startup.
+
+@item @emph{Signals shorted} ... Sometimes a chip, board, or
+adapter will connect SRST to TRST, instead of keeping them separate.
+Use the @command{reset_config} @var{combination} options to say
+when those signals aren't properly independent.
+
+@item @emph{Timing} ... Reset circuitry like a resistor/capacitor
+delay circuit, reset supervisor, or on-chip features can extend
+the effect of a JTAG adapter's reset for some time after the adapter
+stops issuing the reset. For example, there may be chip or board
+requirements that all reset pulses last for at least a
+certain amount of time; and reset buttons commonly have
+hardware debouncing.
+Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
+commands to say when extra delays are needed.
+
+@item @emph{Drive type} ... Reset lines often have a pullup
+resistor, letting the JTAG interface treat them as open-drain
+signals. But that's not a requirement, so the adapter may need
+to use push/pull output drivers.
+Also, with weak pullups it may be advisable to drive
+signals to both levels (push/pull) to minimize rise times.
+Use the @command{reset_config} @var{trst_type} and
+@var{srst_type} parameters to say how to drive reset signals.
+@end itemize
+
+There can also be other issues.
+Some devices don't fully conform to the JTAG specifications.
+Others have chip-specific extensions like extra steps needed
+during TAP reset, or a requirement to use the normally-optional TRST
+signal.
+Trivial system-specific differences are common, such as
+SRST and TRST using slightly different names.
+
+@section Commands for Handling Resets
+
+@deffn {Command} jtag_nsrst_delay milliseconds
+How long (in milliseconds) OpenOCD should wait after deasserting
+nSRST (active-low system reset) before starting new JTAG operations.
+When a board has a reset button connected to SRST line it will
+probably have hardware debouncing, implying you should use this.
+@end deffn
+
+@deffn {Command} jtag_ntrst_delay milliseconds
+How long (in milliseconds) OpenOCD should wait after deasserting
+nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
+@end deffn
+
+@deffn {Command} reset_config signals [combination [trst_type [srst_type]]]
+This command tells OpenOCD the reset configuration
+of your combination of JTAG interface, board, and target.
+If the JTAG interface provides SRST, but the board doesn't connect
+that signal properly, then OpenOCD can't use it. @var{signals} can
be @option{none}, @option{trst_only}, @option{srst_only} or
@option{trst_and_srst}.
-[@var{combination}] is an optional value specifying broken reset
+The @var{combination} is an optional value specifying broken reset
signal implementations. @option{srst_pulls_trst} states that the
-testlogic is reset together with the reset of the system (e.g. Philips
+test logic is reset together with the reset of the system (e.g. Philips
LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
the system is reset together with the test logic (only hypothetical, I
haven't seen hardware with such a bug, and can be worked around).
-@option{combined} imples both @option{srst_pulls_trst} and
+@option{combined} implies both @option{srst_pulls_trst} and
@option{trst_pulls_srst}. The default behaviour if no option given is
@option{separate}.
-The [@var{trst_type}] and [@var{srst_type}] parameters allow the
+The optional @var{trst_type} and @var{srst_type} parameters allow the
driver type of the reset lines to be specified. Possible values are
@option{trst_push_pull} (default) and @option{trst_open_drain} for the
test reset signal, and @option{srst_open_drain} (default) and
@option{srst_push_pull} for the system reset. These values only affect
JTAG interfaces with support for different drivers, like the Amontec
JTAGkey and JTAGAccelerator.
-
-@comment - end command
-@end itemize
-
+@end deffn
@node Tap Creation
Tap Uses:
@itemize @bullet
@item @b{Debug Target} A tap can be used by a GDB debug target
-@item @b{Flash Programing} Some chips program the flash via JTAG
-@item @b{Boundry Scan} Some chips support boundry scan.
+@item @b{Flash Programing} Some chips program the flash directly via JTAG,
+instead of indirectly by making a CPU do it.
+@item @b{Boundry Scan} Some chips support boundary scan.
@end itemize
parameters'', the required parameters are:
@comment START REQUIRED
@itemize @bullet
-@item @b{-irlen NUMBER} - the length in bits of the instruction register
-@item @b{-ircapture NUMBER} - the ID code capture command.
-@item @b{-irmask NUMBER} - the corresponding mask for the ir register.
+@item @b{-irlen NUMBER} - the length in bits of the instruction register, mostly 4 or 5 bits.
+@item @b{-ircapture NUMBER} - the IDCODE capture command, usually 0x01.
+@item @b{-irmask NUMBER} - the corresponding mask for the IR register. For
+some devices, there are bits in the IR that aren't used. This lets you mask
+them off when doing comparisons. In general, this should just be all ones for
+the size of the IR.
@comment END REQUIRED
@end itemize
An example of a FOOBAR Tap
bits long, during Capture-IR 0x42 is loaded into the IR, and bits
[6,4,2,0] are checked.
-FIXME: The IDCODE - this was not used in the old code, it should be?
-Right? -Duane.
@item @b{Optional configparams}
@comment START Optional
@itemize @bullet
@item @b{-expected-id NUMBER}
@* By default it is zero. If non-zero represents the
-expected tap ID used when the Jtag Chain is examined. See below.
+expected tap ID used when the JTAG chain is examined. Repeat
+the option as many times as required if multiple id's can be
+expected. See below.
@item @b{-disable}
@item @b{-enable}
@* By default not specified the tap is enabled. Some chips have a
-jtag route controller (JRC) that is used to enable and/or disable
-specific jtag taps. You can later enable or disable any JTAG tap via
+JTAG route controller (JRC) that is used to enable and/or disable
+specific JTAG taps. You can later enable or disable any JTAG tap via
the command @b{jtag tapenable DOTTED.NAME} or @b{jtag tapdisable
DOTTED.NAME}
@comment END Optional
@* newtap is a sub command of the ``jtag'' command
@item @b{Big Picture Background}
@*GDB Talks to OpenOCD using the GDB protocol via
-tcpip. OpenOCD then uses the JTAG interface (the dongle) to
+TCP/IP. OpenOCD then uses the JTAG interface (the dongle) to
control the JTAG chain on your board. Your board has one or more chips
in a @i{daisy chain configuration}. Each chip may have one or more
-jtag taps. GDB ends up talking via OpenOCD to one of the taps.
+JTAG taps. GDB ends up talking via OpenOCD to one of the taps.
@item @b{NAME Rules}
@*Names follow ``C'' symbol name rules (start with alpha ...)
@item @b{TAPNAME - Conventions}
@itemize @bullet
@item @b{tap} - should be used only FPGA or CPLD like devices with a single tap.
-@item @b{cpu} - the main cpu of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
+@item @b{cpu} - the main CPU of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
@item @b{flash} - if the chip has a flash tap, example: str912.flash
@item @b{bs} - for boundary scan if this is a seperate tap.
-@item @b{jrc} - for jtag route controller (example: OMAP3530 found on Beagleboards)
+@item @b{etb} - for an embedded trace buffer (example: an ARM ETB11)
+@item @b{jrc} - for JTAG route controller (example: OMAP3530 found on Beagleboards)
@item @b{unknownN} - where N is a number if you have no idea what the tap is for
@item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
-@item @b{When in doubt} - use the chip makers name in their data sheet.
+@item @b{When in doubt} - use the chip maker's name in their data sheet.
@end itemize
@item @b{DOTTED.NAME}
@* @b{CHIPNAME}.@b{TAPNAME} creates the tap name, aka: the
@item @b{Multi Tap Example}
@* This example is based on the ST Microsystems STR912. See the ST
document titled: @b{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
-28/102, Figure 3: Jtag chaining inside the STR91xFA}.
+28/102, Figure 3: JTAG chaining inside the STR91xFA}.
@url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}
@*@b{checked: 28/nov/2008}
-The diagram shows the TDO pin connects to the flash tap, flash TDI
+The diagram shows that the TDO pin connects to the flash tap, flash TDI
connects to the CPU debug tap, CPU TDI connects to the boundary scan
tap which then connects to the TDI pin.
@item @b{Note: Deprecated} - Index Numbers
@* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
feature is still present, however its use is highly discouraged and
-should not be counted upon.
+should not be counted upon. Update all of your scripts to use
+TAP names rather than numbers.
@item @b{Multiple chips}
@* If your board has multiple chips, you should be
able to @b{source} two configuration files, in the proper order, and
@* @b{Removed: 28/nov/2008} This command has been removed and replaced
by the ``jtag newtap'' command. The documentation remains here so that
one can easily convert the old syntax to the new syntax. About the old
-syntax: The old syntax is positional, ie: The 4th parameter is the
+syntax: The old syntax is positional, i.e.: The 3rd parameter is the
``irmask''. The new syntax requires named prefixes, and supports
-additional options, for example ``-irmask 4''. Please refer to the
+additional options, for example ``-expected-id 0x3f0f0f0f''. Please refer to the
@b{jtag newtap} command for details.
@example
-OLD: jtag_device 8 0x01 0x0e3 0xfe
-NEW: jtag newtap CHIPNAME TAPNAME -irlen 8 -ircapture 0xe3 -irmask 0xfe
+OLD: jtag_device 8 0x01 0xe3 0xfe
+NEW: jtag newtap CHIPNAME TAPNAME -irlen 8 -ircapture 0x01 -irmask 0xe3
@end example
@section Enable/Disable Taps
@cindex JRC
@cindex route controller
-These commands are used when your target has a JTAG Route controller
-that effectively adds or removes a tap from the jtag chain in a
+These commands are used when your target has a JTAG route controller
+that effectively adds or removes a tap from the JTAG chain in a
non-standard way.
The ``standard way'' to remove a tap would be to place the tap in
bypass mode. But with the advent of modern chips, this is not always a
good solution. Some taps operate slowly, others operate fast, and
-there are other JTAG clock syncronization problems one must face. To
-solve that problem, the JTAG Route controller was introduced. Rather
-then ``bypass'' the tap, the tap is completely removed from the
+there are other JTAG clock synchronisation problems one must face. To
+solve that problem, the JTAG route controller was introduced. Rather
+than ``bypass'' the tap, the tap is completely removed from the
circuit and skipped.
-From OpenOCD's view point, a JTAG TAP is in one of 3 states:
+From OpenOCD's point of view, a JTAG tap is in one of 3 states:
@itemize @bullet
@item @b{Enabled - Not In ByPass} and has a variable bit length
This command returns 1 if the named tap is currently enabled, 0 if not.
This command exists so that scripts that manipulate a JRC (like the
-Omap3530 has) can determine if OpenOCD thinks a tap is presently
-enabled, or disabled.
+OMAP3530 has) can determine if OpenOCD thinks a tap is presently
+enabled or disabled.
@page
@node Target Configuration
@chapter Target Configuration
+@cindex GDB target
-This chapter discusses how to create a GDB Debug Target. Before
-creating a ``target'' a JTAG Tap DOTTED.NAME must exist first.
+This chapter discusses how to create a GDB debug target. Before
+creating a ``target'' a JTAG tap DOTTED.NAME must exist first.
@section targets [NAME]
@b{Note:} This command name is PLURAL - not singular.
With NO parameter, this plural @b{targets} command lists all known
targets in a human friendly form.
-With a parameter, this pural @b{targets} command sets the current
-target to the given name. (ie: If there are multiple debug targets)
+With a parameter, this plural @b{targets} command sets the current
+target to the given name. (i.e.: If there are multiple debug targets)
Example:
@verbatim
The TARGET command accepts these sub-commands:
@itemize @bullet
@item @b{create} .. parameters ..
-@* creates a new target, See below for details.
+@* creates a new target, see below for details.
@item @b{types}
@* Lists all supported target types (perhaps some are not yet in this document).
@item @b{names}
@b{Model:} The Tcl/Tk language has the concept of object commands. A
good example is a on screen button, once a button is created a button
-has a name (a path in TK terms) and that name is useable as a 1st
-class command. For example in TK, one can create a button and later
+has a name (a path in Tk terms) and that name is useable as a 1st
+class command. For example in Tk, one can create a button and later
configure it like this:
@example
@end example
In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
-button. Commands avaialble as a ``target object'' are:
+button. Commands available as a ``target object'' are:
@comment START targetobj commands.
@itemize @bullet
@item @b{configure} - configure the target; see Target Config/Cget Options below
@item @b{cget} - query the target configuration; see Target Config/Cget Options below
-@item @b{curstate} - current target state (running, halt, etc)
+@item @b{curstate} - current target state (running, halt, etc.
@item @b{eventlist}
@* Intended for a human to see/read the currently configure target events.
@item @b{Various Memory Commands} See the ``mww'' command elsewhere.
@end itemize
@section Target Events
+@cindex events
+@anchor{Target Events}
At various times, certain things can happen, or you want them to happen.
Examples:
via ``$_TARGETNAME configure'' see this example.
Syntactially, the option is: ``-event NAME BODY'' where NAME is a
-target event name, and BODY is a tcl procedure or string of commands
+target event name, and BODY is a Tcl procedure or string of commands
to execute.
The programmers model is the ``-command'' option used in Tcl/Tk
The following events are available:
@itemize @bullet
@item @b{debug-halted}
-@* The target has halted for debug reasons (ie: breakpoint)
+@* The target has halted for debug reasons (i.e.: breakpoint)
@item @b{debug-resumed}
-@* The target has resumed (ie: gdb said run)
+@* The target has resumed (i.e.: gdb said run)
@item @b{early-halted}
@* Occurs early in the halt process
@item @b{examine-end}
@item @b{gdb-flash-write-end}
@* After GDB writes to the flash
@item @b{gdb-start}
-@* Before the taret steps, gdb is trying to start/resume the tarfget
+@* Before the taret steps, gdb is trying to start/resume the target
@item @b{halted}
@* The target has halted
@item @b{old-gdb_program_config}
@item @b{reset-halt-pre}
@* Currently not used
@item @b{reset-init}
-@* Currently not used
+@* Used by @b{reset init} command for board-specific initialization.
+This is where you would configure PLLs and clocking, set up DRAM so
+you can download programs that don't fit in on-chip SRAM, set up pin
+multiplexing, and so on.
@item @b{reset-start}
@* Currently not used
@item @b{reset-wait-pos}
@end example
@end itemize
-
-@section target create
+@section Target Create
+@anchor{Target Create}
@cindex target
@cindex target creation
@itemize @bullet
@item @b{NAME}
@* Is the name of the debug target. By convention it should be the tap
-DOTTED.NAME, this name is also used to create the target object
-command.
+DOTTED.NAME. This name is also used to create the target object
+command, and in other places the target needs to be identified.
@item @b{TYPE}
-@* Specifies the target type, ie: arm7tdmi, or cortexM3. Currently supported targes are:
+@* Specifies the target type, i.e.: ARM7TDMI, or Cortex-M3. Currently supported targets are:
@comment START types
@itemize @minus
@item @b{arm7tdmi}
@comment end TYPES
@end itemize
@item @b{PARAMS}
-@*PARAMs are various target configure parameters, the following are mandatory
-at configuration:
+@*PARAMs are various target configuration parameters. The following ones are mandatory:
@comment START mandatory
@itemize @bullet
@item @b{-endian big|little}
@section Target Config/Cget Options
These options can be specified when the target is created, or later
via the configure option or to query the target via cget.
+
+You should specify a working area if you can; typically it uses some
+on-chip SRAM. Such a working area can speed up many things, including bulk
+writes to target memory; flash operations like checking to see if memory needs
+to be erased; GDB memory checksumming; and may help perform otherwise
+unavailable operations (like some coprocessor operations on ARM7/9 systems).
@itemize @bullet
@item @b{-type} - returns the target type
@item @b{-event NAME BODY} see Target events
-@item @b{-work-area-virt [ADDRESS]} specify/set the work area
-@item @b{-work-area-phys [ADDRESS]} specify/set the work area
+@item @b{-work-area-virt [ADDRESS]} specify/set the work area base address
+which will be used when an MMU is active.
+@item @b{-work-area-phys [ADDRESS]} specify/set the work area base address
+which will be used when an MMU is inactive.
@item @b{-work-area-size [ADDRESS]} specify/set the work area
-@item @b{-work-area-backup [0|1]} does the work area get backed up
+@item @b{-work-area-backup [0|1]} does the work area get backed up;
+by default, it doesn't. When possible, use a working_area that doesn't
+need to be backed up, since performing a backup slows down operations.
@item @b{-endian [big|little]}
-@item @b{-variant [NAME]} some chips have varients OpenOCD needs to know about
+@item @b{-variant [NAME]} some chips have variants OpenOCD needs to know about
@item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
@end itemize
Example:
@}
@end example
-@section Target Varients
+@section Target Variants
@itemize @bullet
@item @b{arm7tdmi}
@* Unknown (please write me)
@item @b{arm720t}
-@* Unknown (please write me) (simular to arm7tdmi)
+@* Unknown (please write me) (similar to arm7tdmi)
@item @b{arm9tdmi}
-@* Varients: @option{arm920t}, @option{arm922t} and @option{arm940t}
+@* Variants: @option{arm920t}, @option{arm922t} and @option{arm940t}
This enables the hardware single-stepping support found on these
cores.
@item @b{arm920t}
@item @b{arm966e}
@* None (this is also used as the ARM946)
@item @b{cortex_m3}
-@* use variant <@var{-variant lm3s}> when debugging luminary lm3s targets. This will cause
+@* use variant <@var{-variant lm3s}> when debugging Luminary lm3s targets. This will cause
OpenOCD to use a software reset rather than asserting SRST to avoid a issue with clearing
the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
be detected and the normal reset behaviour used.
OpenOCD to instead use an EJTAG software reset command to reset the
processor. You still need to enable @option{srst} on the reset
configuration command to enable OpenOCD hardware reset functionality.
-@comment END varients
+@comment END variants
@end itemize
@section working_area - Command Removed
@cindex working_area
@end example
@* The target# is a the 0 based target numerical index.
-This command specifies a working area for the debugger to use. This
-may be used to speed-up downloads to target memory and flash
-operations, or to perform otherwise unavailable operations (some
-coprocessor operations on ARM7/9 systems, for example). The last
-parameter decides whether the memory should be preserved
-(<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If
-possible, use a working_area that doesn't need to be backed up, as
-performing a backup slows down operation.
-
@node Flash Configuration
-@chapter Flash Programing
+@chapter Flash programming
@cindex Flash Configuration
+OpenOCD has different commands for NOR and NAND flash;
+the ``flash'' command works with NOR flash, while
+the ``nand'' command works with NAND flash.
+This partially reflects different hardware technologies:
+NOR flash usually supports direct CPU instruction and data bus access,
+while data from a NAND flash must be copied to memory before it can be
+used. (SPI flash must also be copied to memory before use.)
+However, the documentation also uses ``flash'' as a generic term;
+for example, ``Put flash configuration in board-specific files''.
+
@b{Note:} As of 28/nov/2008 OpenOCD does not know how to program a SPI
-flash that a micro may boot from. Perhaps you the reader would like to
+flash that a micro may boot from. Perhaps you, the reader, would like to
contribute support for this.
Flash Steps:
flash on your board.
@item GDB Flashing
@* Flashing via GDB requires the flash be configured via ``flash
-bank'', and the GDB flash features be enabled. See the Daemon
-configuration section for more details.
+bank'', and the GDB flash features be enabled.
+@xref{GDB Configuration}.
@end enumerate
@section Flash commands
@example
@b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
-<@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
+<@var{bus_width}> <@var{target}> [@var{driver_options ...}]
@end example
@cindex flash bank
@*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
@subsection External Flash - cfi options
@cindex cfi options
-CFI flash are external flash chips - often they are connected to a
-specific chip select on the micro. By default at hard reset most
-micros have the ablity to ``boot'' from some flash chip - typically
-attached to the chips CS0 pin.
+CFI flashes are external flash chips - often they are connected to a
+specific chip select on the CPU. By default, at hard reset, most
+CPUs have the ablity to ``boot'' from some flash chip - typically
+attached to the CPU's CS0 pin.
For other chip selects: OpenOCD does not know how to configure, or
-access a specific chip select. Instead you the human might need to via
-other commands (like: mww) configure additional chip selects, or
+access a specific chip select. Instead you, the human, might need to
+configure additional chip selects via other commands (like: mww) , or
perhaps configure a GPIO pin that controls the ``write protect'' pin
-on the FLASH chip.
+on the flash chip.
@b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
-<@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
-@*CFI flashes require the number of the target they're connected to as an additional
+<@var{target}> [@var{jedec_probe}|@var{x16_as_x8}]
+@*CFI flashes require the name or number of the target they're connected to
+as an additional
argument. The CFI driver makes use of a working area (specified for the target)
to significantly speed up operation.
@var{chip_width} and @var{bus_width} are specified in bytes.
-The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
+The @var{jedec_probe} option is used to detect certain non-CFI flash ROMs, like AM29LV010 and similar types.
@var{x16_as_x8} ???
-@subsection Internal Flash (Micro Controllers)
+@subsection Internal Flash (Microcontrollers)
@subsubsection lpc2000 options
@cindex lpc2000 options
-@b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
+@b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
<@var{clock}> [@var{calc_checksum}]
@*LPC flashes don't require the chip and bus width to be specified. Additional
parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
-or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
-of the target this flash belongs to (first is 0), the frequency at which the core
+or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx),
+the name or number of the target this flash belongs to (first is 0),
+the frequency at which the core
is currently running (in kHz - must be an integral number), and the optional keyword
@var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
vector table.
@subsubsection at91sam7 options
@cindex at91sam7 options
-@b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
-@*AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
+@b{flash bank at91sam7} 0 0 0 0 <@var{target}>
+@*AT91SAM7 flashes only require the @var{target}, all other values are looked up after
reading the chip-id and type.
@subsubsection str7 options
@cindex str7 options
-@b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
+@b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
@*variant can be either STR71x, STR73x or STR75x.
@subsubsection str9 options
@cindex str9 options
-@b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*The str9 needs the flash controller to be configured prior to Flash programming, eg.
+@b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target}>
+@*The str9 needs the flash controller to be configured prior to Flash programming, e.g.
@example
str9x flash_config 0 4 2 0 0x80000
@end example
@subsubsection str9 options (str9xpec driver)
-@b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*Before using the flash commands the turbo mode will need enabling using str9xpec
+@b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target}>
+@*Before using the flash commands the turbo mode must be enabled using str9xpec
@option{enable_turbo} <@var{num>.}
Only use this driver for locking/unlocking the device or configuring the option bytes.
Use the standard str9 driver for programming. @xref{STR9 specific commands}.
-@subsubsection stellaris (LM3Sxxx) options
-@cindex stellaris (LM3Sxxx) options
+@subsubsection Stellaris (LM3Sxxx) options
+@cindex Stellaris (LM3Sxxx) options
-@b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*stellaris flash plugin only require the @var{target#}.
+@b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target}>
+@*Stellaris flash plugin only require the @var{target}.
@subsubsection stm32x options
@cindex stm32x options
-@b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*stm32x flash plugin only require the @var{target#}.
+@b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target}>
+@*stm32x flash plugin only require the @var{target}.
@subsubsection aduc702x options
@cindex aduc702x options
-@b{flash bank aduc702x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*aduc702x flash plugin require the flash @var{base}, @var{size} and @var{target#}.
+@b{flash bank aduc702x} 0 0 0 0 <@var{target}>
+@*The aduc702x flash plugin works with Analog Devices model numbers ADUC7019 through ADUC7028. The setup command only requires the @var{target} argument (all devices in this family have the same memory layout).
-@subsection mFlash configuration
-@cindex mFlash configuration
+@subsection mFlash Configuration
+@cindex mFlash Configuration
@b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
-<@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target #}>
+<@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target}>
@cindex mflash bank
@*Configures a mflash for <@var{soc}> host bank at
<@var{base}>. <@var{chip_width}> and <@var{bus_width}> are bytes
mflash bank pxa270 0x08000000 2 2 43 -1 51 0
@end example
-@section Micro Controller Specific Flash Commands
+@section Microcontroller specific Flash Commands
@subsection AT91SAM7 specific commands
@cindex AT91SAM7 specific commands
The flash configuration is deduced from the chip identification register. The flash
-controller handles erases automatically on a page (128/265 byte) basis so erase is
+controller handles erases automatically on a page (128/265 byte) basis, so erase is
not necessary for flash programming. AT91SAM7 processors with less than 512K flash
only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
that can be erased separatly. Only an EraseAll command is supported by the controller
@itemize @bullet
@item @b{str9xpec enable_turbo} <@var{num}>
@cindex str9xpec enable_turbo
-@*enable turbo mode, simply this will remove the str9 from the chain and talk
+@*enable turbo mode, will simply remove the str9 from the chain and talk
directly to the embedded flash controller.
@item @b{str9xpec disable_turbo} <@var{num}>
@cindex str9xpec disable_turbo
-@*restore the str9 into jtag chain.
+@*restore the str9 into JTAG chain.
@item @b{str9xpec lock} <@var{num}>
@cindex str9xpec lock
@*lock str9 device. The str9 will only respond to an unlock command that will
Standard driver @option{str9x} programmed via the str9 core. Normally used for
flash programming as it is faster than the @option{str9xpec} driver.
@item
-Direct programming @option{str9xpec} using the flash controller, this is
+Direct programming @option{str9xpec} using the flash controller. This is an
ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
core does not need to be running to program using this flash driver. Typical use
for this driver is locking/unlocking the target and programming the option bytes.
@end enumerate
-Before we run any cmds using the @option{str9xpec} driver we must first disable
+Before we run any commands using the @option{str9xpec} driver we must first disable
the str9 core. This example assumes the @option{str9xpec} driver has been
configured for flash bank 0.
@example
The above example will read the str9 option bytes.
When performing a unlock remember that you will not be able to halt the str9 - it
has been locked. Halting the core is not required for the @option{str9xpec} driver
-as mentioned above, just issue the cmds above manually or from a telnet prompt.
+as mentioned above, just issue the commands above manually or from a telnet prompt.
@subsection STR9 configuration
@cindex STR9 configuration
@cindex str9x flash_config
@*Configure str9 flash controller.
@example
-eg. str9x flash_config 0 4 2 0 0x80000
+e.g. str9x flash_config 0 4 2 0 0x80000
This will setup
BBSR - Boot Bank Size register
NBBSR - Non Boot Bank Size register
@*mass erase flash memory.
@end itemize
-
+@node NAND Flash Commands
+@chapter NAND Flash Commands
+@cindex NAND
+
+Compared to NOR or SPI flash, NAND devices are inexpensive
+and high density. Today's NAND chips, and multi-chip modules,
+commonly hold multiple GigaBytes of data.
+
+NAND chips consist of a number of ``erase blocks'' of a given
+size (such as 128 KBytes), each of which is divided into a
+number of pages (of perhaps 512 or 2048 bytes each). Each
+page of a NAND flash has an ``out of band'' (OOB) area to hold
+Error Correcting Code (ECC) and other metadata, usually 16 bytes
+of OOB for every 512 bytes of page data.
+
+One key characteristic of NAND flash is that its error rate
+is higher than that of NOR flash. In normal operation, that
+ECC is used to correct and detect errors. However, NAND
+blocks can also wear out and become unusable; those blocks
+are then marked "bad". NAND chips are even shipped from the
+manufacturer with a few bad blocks. The highest density chips
+use a technology (MLC) that wears out more quickly, so ECC
+support is increasingly important as a way to detect blocks
+that have begun to fail, and help to preserve data integrity
+with techniques such as wear leveling.
+
+Software is used to manage the ECC. Some controllers don't
+support ECC directly; in those cases, software ECC is used.
+Other controllers speed up the ECC calculations with hardware.
+Single-bit error correction hardware is routine. Controllers
+geared for newer MLC chips may correct 4 or more errors for
+every 512 bytes of data.
+
+You will need to make sure that any data you write using
+OpenOCD includes the apppropriate kind of ECC. For example,
+that may mean passing the @code{oob_softecc} flag when
+writing NAND data, or ensuring that the correct hardware
+ECC mode is used.
+
+The basic steps for using NAND devices include:
+@enumerate
+@item Declare via the command @command{nand device}
+@* Do this in a board-specific configuration file,
+passing parameters as needed by the controller.
+@item Configure each device using @command{nand probe}.
+@* Do this only after the associated target is set up,
+such as in its reset-init script or in procures defined
+to access that device.
+@item Operate on the flash via @command{nand subcommand}
+@* Often commands to manipulate the flash are typed by a human, or run
+via a script in some automated way. Common task include writing a
+boot loader, operating system, or other data needed to initialize or
+de-brick a board.
+@end enumerate
+
+@b{NOTE:} At the time this text was written, the largest NAND
+flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
+This is because the variables used to hold offsets and lengths
+are only 32 bits wide.
+(Larger chips may work in some cases, unless an offset or length
+is larger than 0xffffffff, the largest 32-bit unsigned integer.)
+Some larger devices will work, since they are actually multi-chip
+modules with two smaller chips and individual chipselect lines.
+
+@section NAND Configuration Commands
+@cindex NAND configuration
+
+NAND chips must be declared in configuration scripts,
+plus some additional configuration that's done after
+OpenOCD has initialized.
+
+@deffn {Config Command} {nand device} controller target [configparams...]
+Declares a NAND device, which can be read and written to
+after it has been configured through @command{nand probe}.
+In OpenOCD, devices are single chips; this is unlike some
+operating systems, which may manage multiple chips as if
+they were a single (larger) device.
+In some cases, configuring a device will activate extra
+commands; see the controller-specific documentation.
+
+@b{NOTE:} This command is not available after OpenOCD
+initialization has completed. Use it in board specific
+configuration files, not interactively.
+
+@itemize @bullet
+@item @var{controller} ... identifies a the controller driver
+associated with the NAND device being declared.
+@xref{NAND Driver List}.
+@item @var{target} ... names the target used when issuing
+commands to the NAND controller.
+@comment Actually, it's currently a controller-specific parameter...
+@item @var{configparams} ... controllers may support, or require,
+additional parameters. See the controller-specific documentation
+for more information.
+@end itemize
+@end deffn
+
+@deffn Command {nand list}
+Prints a one-line summary of each device declared
+using @command{nand device}, numbered from zero.
+Note that un-probed devices show no details.
+@end deffn
+
+@deffn Command {nand probe} num
+Probes the specified device to determine key characteristics
+like its page and block sizes, and how many blocks it has.
+The @var{num} parameter is the value shown by @command{nand list}.
+You must (successfully) probe a device before you can use
+it with most other NAND commands.
+@end deffn
+
+@section Erasing, Reading, Writing to NAND Flash
+
+@deffn Command {nand dump} num filename offset length [oob_option]
+@cindex NAND reading
+Reads binary data from the NAND device and writes it to the file,
+starting at the specified offset.
+The @var{num} parameter is the value shown by @command{nand list}.
+
+Use a complete path name for @var{filename}, so you don't depend
+on the directory used to start the OpenOCD server.
+
+The @var{offset} and @var{length} must be exact multiples of the
+device's page size. They describe a data region; the OOB data
+associated with each such page may also be accessed.
+
+@b{NOTE:} At the time this text was written, no error correction
+was done on the data that's read, unless raw access was disabled
+and the underlying NAND controller driver had a @code{read_page}
+method which handled that error correction.
+
+By default, only page data is saved to the specified file.
+Use an @var{oob_option} parameter to save OOB data:
+@itemize @bullet
+@item no oob_* parameter
+@*Output file holds only page data; OOB is discarded.
+@item @code{oob_raw}
+@*Output file interleaves page data and OOB data;
+the file will be longer than "length" by the size of the
+spare areas associated with each data page.
+Note that this kind of "raw" access is different from
+what's implied by @command{nand raw_access}, which just
+controls whether a hardware-aware access method is used.
+@item @code{oob_only}
+@*Output file has only raw OOB data, and will
+be smaller than "length" since it will contain only the
+spare areas associated with each data page.
+@end itemize
+@end deffn
+
+@deffn Command {nand erase} num offset length
+@cindex NAND erasing
+Erases blocks on the specified NAND device, starting at the
+specified @var{offset} and continuing for @var{length} bytes.
+Both of those values must be exact multiples of the device's
+block size, and the region they specify must fit entirely in the chip.
+The @var{num} parameter is the value shown by @command{nand list}.
+
+@b{NOTE:} This command will try to erase bad blocks, when told
+to do so, which will probably invalidate the manufacturer's bad
+block marker.
+For the remainder of the current server session, @command{nand info}
+will still report that the block ``is'' bad.
+@end deffn
+
+@deffn Command {nand write} num filename offset [option...]
+@cindex NAND writing
+Writes binary data from the file into the specified NAND device,
+starting at the specified offset. Those pages should already
+have been erased; you can't change zero bits to one bits.
+The @var{num} parameter is the value shown by @command{nand list}.
+
+Use a complete path name for @var{filename}, so you don't depend
+on the directory used to start the OpenOCD server.
+
+The @var{offset} must be an exact multiple of the device's page size.
+All data in the file will be written, assuming it doesn't run
+past the end of the device.
+Only full pages are written, and any extra space in the last
+page will be filled with 0xff bytes. (That includes OOB data,
+if that's being written.)
+
+@b{NOTE:} At the time this text was written, bad blocks are
+ignored. That is, this routine will not skip bad blocks,
+but will instead try to write them. This can cause problems.
+
+Provide at most one @var{option} parameter. With some
+NAND drivers, the meanings of these parameters may change
+if @command{nand raw_access} was used to disable hardware ECC.
+@itemize @bullet
+@item no oob_* parameter
+@*File has only page data, which is written.
+If raw acccess is in use, the OOB area will not be written.
+Otherwise, if the underlying NAND controller driver has
+a @code{write_page} routine, that routine may write the OOB
+with hardware-computed ECC data.
+@item @code{oob_only}
+@*File has only raw OOB data, which is written to the OOB area.
+Each page's data area stays untouched. @i{This can be a dangerous
+option}, since it can invalidate the ECC data.
+You may need to force raw access to use this mode.
+@item @code{oob_raw}
+@*File interleaves data and OOB data, both of which are written
+If raw access is enabled, the data is written first, then the
+un-altered OOB.
+Otherwise, if the underlying NAND controller driver has
+a @code{write_page} routine, that routine may modify the OOB
+before it's written, to include hardware-computed ECC data.
+@item @code{oob_softecc}
+@*File has only page data, which is written.
+The OOB area is filled with 0xff, except for a standard 1-bit
+software ECC code stored in conventional locations.
+You might need to force raw access to use this mode, to prevent
+the underlying driver from applying hardware ECC.
+@item @code{oob_softecc_kw}
+@*File has only page data, which is written.
+The OOB area is filled with 0xff, except for a 4-bit software ECC
+specific to the boot ROM in Marvell Kirkwood SoCs.
+You might need to force raw access to use this mode, to prevent
+the underlying driver from applying hardware ECC.
+@end itemize
+@end deffn
+
+@section Other NAND commands
+@cindex NAND other commands
+
+@deffn Command {nand check_bad_blocks} [offset length]
+Checks for manufacturer bad block markers on the specified NAND
+device. If no parameters are provided, checks the whole
+device; otherwise, starts at the specified @var{offset} and
+continues for @var{length} bytes.
+Both of those values must be exact multiples of the device's
+block size, and the region they specify must fit entirely in the chip.
+The @var{num} parameter is the value shown by @command{nand list}.
+
+@b{NOTE:} Before using this command you should force raw access
+with @command{nand raw_access enable} to ensure that the underlying
+driver will not try to apply hardware ECC.
+@end deffn
+
+@deffn Command {nand info} num
+The @var{num} parameter is the value shown by @command{nand list}.
+This prints the one-line summary from "nand list", plus for
+devices which have been probed this also prints any known
+status for each block.
+@end deffn
+
+@deffn Command {nand raw_access} num <enable|disable>
+Sets or clears an flag affecting how page I/O is done.
+The @var{num} parameter is the value shown by @command{nand list}.
+
+This flag is cleared (disabled) by default, but changing that
+value won't affect all NAND devices. The key factor is whether
+the underlying driver provides @code{read_page} or @code{write_page}
+methods. If it doesn't provide those methods, the setting of
+this flag is irrelevant; all access is effectively ``raw''.
+
+When those methods exist, they are normally used when reading
+data (@command{nand dump} or reading bad block markers) or
+writing it (@command{nand write}). However, enabling
+raw access (setting the flag) prevents use of those methods,
+bypassing hardware ECC logic.
+@i{This can be a dangerous option}, since writing blocks
+with the wrong ECC data can cause them to be marked as bad.
+@end deffn
+
+@section NAND Drivers; Driver-specific Options and Commands
+@anchor{NAND Driver List}
+As noted above, the @command{nand device} command allows
+driver-specific options and behaviors.
+Some controllers also activate controller-specific commands.
+
+@deffn {NAND Driver} davinci
+This driver handles the NAND controllers found on DaVinci family
+chips from Texas Instruments.
+It takes three extra parameters:
+address of the NAND chip;
+hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
+address of the AEMIF controller on this processor.
+@example
+nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
+@end example
+All DaVinci processors support the single-bit ECC hardware,
+and newer ones also support the four-bit ECC hardware.
+The @code{write_page} and @code{read_page} methods are used
+to implement those ECC modes, unless they are disabled using
+the @command{nand raw_access} command.
+@end deffn
+
+@deffn {NAND Driver} lpc3180
+These controllers require an extra @command{nand device}
+parameter: the clock rate used by the controller.
+@deffn Command {nand lpc3180 select} num [mlc|slc]
+Configures use of the MLC or SLC controller mode.
+MLC implies use of hardware ECC.
+The @var{num} parameter is the value shown by @command{nand list}.
+@end deffn
+
+At this writing, this driver includes @code{write_page}
+and @code{read_page} methods. Using @command{nand raw_access}
+to disable those methods will prevent use of hardware ECC
+in the MLC controller mode, but won't change SLC behavior.
+@end deffn
+@comment current lpc3180 code won't issue 5-byte address cycles
+
+@deffn {NAND Driver} orion
+These controllers require an extra @command{nand device}
+parameter: the address of the controller.
+@example
+nand device orion 0xd8000000
+@end example
+These controllers don't define any specialized commands.
+At this writing, their drivers don't include @code{write_page}
+or @code{read_page} methods, so @command{nand raw_access} won't
+change any behavior.
+@end deffn
+
+@deffn {NAND Driver} {s3c2410, s3c2412, s3c2440, s3c2443}
+These S3C24xx family controllers don't have any special
+@command{nand device} options, and don't define any
+specialized commands.
+At this writing, their drivers don't include @code{write_page}
+or @code{read_page} methods, so @command{nand raw_access} won't
+change any behavior.
+@end deffn
+
@node General Commands
@chapter General Commands
@cindex commands
The commands documented in this chapter here are common commands that
-you a human may want to type and see the output of. Configuration type
+you, as a human, may want to type and see the output of. Configuration type
commands are documented elsewhere.
Intent:
@item @b{Source Of Commands}
@* OpenOCD commands can occur in a configuration script (discussed
elsewhere) or typed manually by a human or supplied programatically,
-or via one of several Tcp/Ip Ports.
+or via one of several TCP/IP Ports.
@item @b{From the human}
-@* A human should interact with the Telnet interface (default port: 4444,
-or via GDB, default port 3333)
+@* A human should interact with the telnet interface (default port: 4444)
+or via GDB (default port 3333).
To issue commands from within a GDB session, use the @option{monitor}
command, e.g. use @option{monitor poll} to issue the @option{poll}
command. All output is relayed through the GDB session.
@item @b{Machine Interface}
-The TCL interface intent is to be a machine interface. The default TCL
+The Tcl interface's intent is to be a machine interface. The default Tcl
port is 5555.
@end itemize
@subsection shutdown
@cindex shutdown
-@*Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
+@*Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
@subsection debug_level [@var{n}]
@cindex debug_level
openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
@end example
+@subsection echo <@var{message}>
+@cindex echo
+@*Output message to stdio. e.g. echo "Programming - please wait"
+
@subsection log_output <@var{file}>
@cindex log_output
@*Redirect logging to <file> (default: stderr)
@subsection script <@var{file}>
@cindex script
@*Execute commands from <file>
-Also see: ``source [find FILENAME]''
+See also: ``source [find FILENAME]''
@section Target state handling
@subsection power <@var{on}|@var{off}>
@cindex reg
@*Access a single register by its number[@option{#}] or by its [@option{name}].
No arguments: list all available registers for the current target.
-Number or name argument: display a register
-Number or name and value arguments: set register value
+Number or name argument: display a register.
+Number or name and value arguments: set register value.
@subsection poll [@option{on}|@option{off}]
@cindex poll
@cindex wait_halt
@*Wait for the target to enter debug mode. Optional [@option{ms}] is
a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
-arg given.
+arg is given.
@subsection resume [@var{address}]
@cindex resume
@cindex step
@*Single-step the target at its current code position, or at an optional address.
+@anchor{Reset Command}
@subsection reset [@option{run}|@option{halt}|@option{init}]
@cindex reset
-@*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
-
-With no arguments a "reset run" is executed
+@*Perform a hard-reset. The optional parameter specifies what should
+happen after the reset.
+If there is no parameter, a @command{reset run} is executed.
+The other options will not work on all systems.
+@xref{Reset Configuration}.
@itemize @minus
@item @b{run}
@cindex reset run
@subsection soft_reset_halt
@cindex reset
-@*Requesting target halt and executing a soft reset. This often used
+@*Requesting target halt and executing a soft reset. This is often used
when a target cannot be reset and halted. The target, after reset is
released begins to execute code. OpenOCD attempts to stop the CPU and
-then sets the Program counter back at the reset vector. Unfortunatlly
-that code that was executed may have left hardware in an unknown
+then sets the program counter back to the reset vector. Unfortunately
+the code that was executed may have left the hardware in an unknown
state.
@section Memory access commands
@subsection meminfo
-display available ram memory.
-@subsection Memory Peek/Poke type commands
+display available RAM memory.
+@subsection Memory peek/poke type commands
These commands allow accesses of a specific size to the memory
system. Often these are used to configure the current target in some
special way. For example - one may need to write certian values to the
@enumerate
@item To change the current target see the ``targets'' (plural) command
-@item In system level scripts these commands are depricated, please use the TARGET object versions.
+@item In system level scripts these commands are deprecated, please use the TARGET object versions.
@end enumerate
@itemize @bullet
@*write memory byte (8bit)
@end itemize
-@section Image Loading Commands
+@section Image loading commands
@subsection load_image
@b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
@cindex load_image
@cindex fast_load_image
@anchor{fast_load_image}
@*Normally you should be using @b{load_image} or GDB load. However, for
-testing purposes or when IO overhead is significant(OpenOCD running on embedded
-host), then storing the image in memory and uploading the image to the target
+testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
+host), storing the image in memory and uploading the image to the target
can be a way to upload e.g. multiple debug sessions when the binary does not change.
-Arguments as @b{load_image}, but image is stored in OpenOCD host
+Arguments are the same as @b{load_image}, but the image is stored in OpenOCD host
memory, i.e. does not affect target. This approach is also useful when profiling
-target programming performance as IO and target programming can easily be profiled
-seperately.
+target programming performance as I/O and target programming can easily be profiled
+separately.
@subsection fast_load
@b{fast_load}
@cindex fast_image
@anchor{fast_image}
-@*Loads image stored in memory by @b{fast_load_image} to current target. Must be preceeded by fast_load_image.
+@*Loads an image stored in memory by @b{fast_load_image} to the current target. Must be preceeded by fast_load_image.
@subsection dump_image
@b{dump_image} <@var{file}> <@var{address}> <@var{size}>
@cindex dump_image
@b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
@cindex verify_image
@*Verify <@var{file}> against target memory starting at <@var{address}>.
-This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
+This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
@section Breakpoint commands
@itemize
@item @b{profile} <@var{seconds}> <@var{gmon.out}>
-Profiling samples the CPU PC as quickly as OpenOCD is able, which will be used as a random sampling of PC.
+Profiling samples the CPU's program counter as quickly as possible, which is useful for non-intrusive stochastic profiling.
+
@end itemize
@section Target Specific Commands
@cindex ARM7/9 specific commands
These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
-ARM920t or ARM926EJ-S.
+ARM920T or ARM926EJ-S.
@itemize @bullet
@item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
@cindex arm7_9 dbgrq
@anchor{arm7_9 fast_memory_access}
@*Allow OpenOCD to read and write memory without checking completion of
the operation. This provides a huge speed increase, especially with USB JTAG
-cables (FT2232), but might be unsafe if used with targets running at a very low
-speed, like the 32kHz startup clock of an AT91RM9200.
+cables (FT2232), but might be unsafe if used with targets running at very low
+speeds, like the 32kHz startup clock of an AT91RM9200.
@item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
@cindex arm7_9 dcc_downloads
@*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
-unsafe, especially with targets running at a very low speed. This command was introduced
-with OpenOCD rev. 60.
+unsafe, especially with targets running at very low speeds. This command was introduced
+with OpenOCD rev. 60, and requires a few bytes of working area.
@end itemize
@subsection ARM720T specific commands
@option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
@option{irq} @option{fiq}.
-Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
+Can also be used on other ARM9 based cores such as ARM966, ARM920T and ARM926EJ-S.
@end itemize
@subsection ARM966E specific commands
@*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
@item @b{arm920t cache_info}
@cindex arm920t cache_info
-@*Print information about the caches found. This allows you to see if your target
-is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
+@*Print information about the caches found. This allows to see whether your target
+is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
@item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
@cindex arm920t md<bhw>_phys
@*Display memory at physical address addr.
@*Translate a virtual address to a physical address.
@end itemize
-@subsection ARM926EJS specific commands
-@cindex ARM926EJS specific commands
+@subsection ARM926EJ-S specific commands
+@cindex ARM926EJ-S specific commands
@itemize @bullet
@item @b{arm926ejs cp15} <@var{num}> [@var{value}]
OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
See libdcc in the contrib dir for more details.
@itemize @bullet
-@item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
+@item @b{target_request debugmsgs} <@var{enable}|@var{disable}|@var{charmsg}>
@cindex target_request debugmsgs
-@*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
+@*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running. @var{charmsg} receives messages if Linux kernel ``Kernel low-level debugging via EmbeddedICE DCC channel'' option is enabled.
@end itemize
@node JTAG Commands
@chapter JTAG Commands
-@cindex JTAG commands
+@cindex JTAG Commands
Generally most people will not use the bulk of these commands. They
are mostly used by the OpenOCD developers or those who need to
directly manipulate the JTAG taps.
In general these commands control JTAG taps at a very low level. For
-example if you need to control a JTAG Route Controller (ie: the
+example if you need to control a JTAG Route Controller (i.e.: the
OMAP3530 on the Beagle Board has one) you might use these commands in
a script or an event procedure.
@section Commands
@node TFTP
@chapter TFTP
@cindex TFTP
-If OpenOCD runs on an embedded host(as ZY1000 does), then tftp can
-be used to access files on PCs(either developer PC or some other PC).
+If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
+be used to access files on PCs (either the developer's PC or some other PC).
The way this works on the ZY1000 is to prefix a filename by
-"/tftp/ip/" and append the tftp path on the tftp
-server(tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will
+"/tftp/ip/" and append the TFTP path on the TFTP
+server (tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will
load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
if the file was hosted on the embedded host.
-In order to achieve decent performance, you must choose a tftp server
-that supports a packet size bigger than the default packet size(512 bytes). There
-are numerous tftp servers out there(free and commercial) and you will have to do
+In order to achieve decent performance, you must choose a TFTP server
+that supports a packet size bigger than the default packet size (512 bytes). There
+are numerous TFTP servers out there (free and commercial) and you will have to do
a bit of googling to find something that fits your requirements.
@node Sample Scripts
@chapter Sample Scripts
@cindex scripts
-This page shows how to use the target library.
+This page shows how to use the Target Library.
-The configuration script can be divided in the following section:
+The configuration script can be divided into the following sections:
@itemize @bullet
-@item daemon configuration
-@item interface
-@item jtag scan chain
-@item target configuration
-@item flash configuration
+@item Daemon configuration
+@item Interface
+@item JTAG scan chain
+@item Target configuration
+@item Flash configuration
@end itemize
Detailed information about each section can be found at OpenOCD configuration.
@node GDB and OpenOCD
@chapter GDB and OpenOCD
-@cindex GDB and OpenOCD
+@cindex GDB
OpenOCD complies with the remote gdbserver protocol, and as such can be used
to debug remote targets.
@cindex Connecting to GDB
@anchor{Connecting to GDB}
Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
-instance 6.3 has a known bug where it produces bogus memory access
+instance GDB 6.3 has a known bug that produces bogus memory access
errors, which has since been fixed: look up 1836 in
@url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
@*OpenOCD can communicate with GDB in two ways:
@enumerate
@item
-A socket (tcp) connection is typically started as follows:
+A socket (TCP/IP) connection is typically started as follows:
@example
target remote localhost:3333
@end example
@item
A pipe connection is typically started as follows:
@example
-target remote openocd --pipe
+target remote | openocd --pipe
@end example
This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
-Using this method has the advantage of GDB starting/stopping OpenOCD for debug session.
+Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
+session.
@end enumerate
@*To see a list of available OpenOCD commands type @option{monitor help} on the
-GDB commandline.
+GDB command line.
OpenOCD supports the gdb @option{qSupported} packet, this enables information
-to be sent by the gdb server (OpenOCD) to GDB. Typical information includes
-packet size and device memory map.
+to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
+packet size and the device's memory map.
Previous versions of OpenOCD required the following GDB options to increase
-the packet size and speed up GDB communication.
+the packet size and speed up GDB communication:
@example
set remote memory-write-packet-size 1024
set remote memory-write-packet-size fixed
@section Programming using GDB
@cindex Programming using GDB
-By default the target memory map is sent to GDB, this can be disabled by
-the following OpenOCD config option:
+By default the target memory map is sent to GDB. This can be disabled by
+the following OpenOCD configuration option:
@example
gdb_memory_map disable
@end example
-For this to function correctly a valid flash config must also be configured
+For this to function correctly a valid flash configuration must also be set
in OpenOCD. For faster performance you should also configure a valid
working area.
Informing GDB of the memory map of the target will enable GDB to protect any
-flash area of the target and use hardware breakpoints by default. This means
-that the OpenOCD option @option{gdb_breakpoint_override} is not required when
+flash areas of the target and use hardware breakpoints by default. This means
+that the OpenOCD option @command{gdb_breakpoint_override} is not required when
using a memory map. @xref{gdb_breakpoint_override}.
-To view the configured memory map in GDB, use the gdb command @option{info mem}
-All other unasigned addresses within GDB are treated as RAM.
+To view the configured memory map in GDB, use the GDB command @option{info mem}
+All other unassigned addresses within GDB are treated as RAM.
-GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
-this can be changed to the old behaviour by using the following GDB command.
+GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
+This can be changed to the old behaviour by using the following GDB command
@example
set mem inaccessible-by-default off
@end example
-If @option{gdb_flash_program enable} is also used, GDB will be able to
+If @command{gdb_flash_program enable} is also used, GDB will be able to
program any flash memory using the vFlash interface.
GDB will look at the target memory map when a load command is given, if any
will be used.
If the target needs configuring before GDB programming, an event
-script can be executed.
+script can be executed:
@example
$_TARGETNAME configure -event EVENTNAME BODY
@end example
To verify any flash programming the GDB command @option{compare-sections}
can be used.
-@node TCL scripting API
-@chapter TCL scripting API
-@cindex TCL scripting API
-API rules
+@node Tcl Scripting API
+@chapter Tcl Scripting API
+@cindex Tcl Scripting API
+@cindex Tcl scripts
+@section API rules
The commands are stateless. E.g. the telnet command line has a concept
of currently active target, the Tcl API proc's take this sort of state
Lists returned must be relatively small. Otherwise a range
should be passed in to the proc in question.
-Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks
+@section Internal low-level Commands
+
+By low-level, the intent is a human would not directly use these commands.
+
+Low-level commands are (should be) prefixed with "openocd_", e.g. openocd_flash_banks
is the low level API upon which "flash banks" is implemented.
@itemize @bullet
@item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
-Read memory and return as a TCL array for script processing
+Read memory and return as a Tcl array for script processing
@item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
-Convert a TCL array to memory locations and write the values
+Convert a Tcl array to memory locations and write the values
@item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
Return information about the flash banks
@end itemize
OpenOCD commands can consist of two words, e.g. "flash banks". The
-startup.tcl "unknown" proc will translate this into a tcl proc
+startup.tcl "unknown" proc will translate this into a Tcl proc
called "flash_banks".
+@section OpenOCD specific Global Variables
+
+@subsection HostOS
+
+Real Tcl has ::tcl_platform(), and platform::identify, and many other
+variables. JimTCL, as implemented in OpenOCD creates $HostOS which
+holds one of the following values:
+
+@itemize @bullet
+@item @b{winxx} Built using Microsoft Visual Studio
+@item @b{linux} Linux is the underlying operating sytem
+@item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
+@item @b{cygwin} Running under Cygwin
+@item @b{mingw32} Running under MingW32
+@item @b{other} Unknown, none of the above.
+@end itemize
+
+Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
@node Upgrading
@chapter Deprecated/Removed Commands
@*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
@item @b{arm7_9 force_hw_bkpts}
@cindex arm7_9 force_hw_bkpts
-@*Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
-for flash if the gdb memory map has been set up(default when flash is declared in
+@*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
+for flash if the GDB memory map has been set up(default when flash is declared in
target configuration). @xref{gdb_breakpoint_override}.
@item @b{arm7_9 sw_bkpts}
@cindex arm7_9 sw_bkpts
-@*On by default. See also @option{gdb_breakpoint_override}. @xref{gdb_breakpoint_override}.
+@*On by default. @xref{gdb_breakpoint_override}.
@item @b{daemon_startup}
@cindex daemon_startup
@*this config option has been removed, simply adding @option{init} and @option{reset halt} to
@item @b{flash auto_erase}
@cindex flash auto_erase
@*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
+
+@item @b{jtag_speed} value
+@*@xref{JTAG Speed}.
+Usually, a value of zero means maximum
+speed. The actual effect of this option depends on the JTAG interface used.
+@itemize @minus
+@item wiggler: maximum speed / @var{number}
+@item ft2232: 6MHz / (@var{number}+1)
+@item amt jtagaccel: 8 / 2**@var{number}
+@item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
+@item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
+@comment end speed list.
+@end itemize
+
@item @b{load_binary}
@cindex load_binary
@*use @option{load_image} command with same args. @xref{load_image}.
@cindex faq
@enumerate
@item @b{RTCK, also known as: Adaptive Clocking - What is it?}
+@anchor{FAQ RTCK}
@cindex RTCK
@cindex adaptive clocking
@*
In digital circuit design it is often refered to as ``clock
-syncronization'' the JTAG interface uses one clock (TCK or TCLK)
+synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
operating at some speed, your target is operating at another. The two
-clocks are not syncronized, they are ``asynchronous''
+clocks are not synchronised, they are ``asynchronous''
-In order for the two to work together they must syncronize. Otherwise
+In order for the two to work together they must be synchronised. Otherwise
the two systems will get out of sync with each other and nothing will
-work. There are 2 basic options. @b{1.} use a special circuit or
-@b{2.} one clock must be some multile slower the the other.
+work. There are 2 basic options:
+@enumerate
+@item
+Use a special circuit.
+@item
+One clock must be some multiple slower than the other.
+@end enumerate
@b{Does this really matter?} For some chips and some situations, this
-is a non-issue (ie: A 500mhz ARM926) but for others - for example some
-ATMEL SAM7 and SAM9 chips start operation from reset at 32khz -
+is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
+Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
program/enable the oscillators and eventually the main clock. It is in
-those critical times you must slow the jtag clock to sometimes 1 to
-4khz.
+those critical times you must slow the JTAG clock to sometimes 1 to
+4kHz.
-Imagine debugging that 500mhz arm926 hand held battery powered device
-that ``deep sleeps'' at 32khz between every keystroke. It can be
+Imagine debugging a 500MHz ARM926 hand held battery powered device
+that ``deep sleeps'' at 32kHz between every keystroke. It can be
painful.
@b{Solution #1 - A special circuit}
-In order to make use of this your jtag dongle must support the RTCK
+In order to make use of this, your JTAG dongle must support the RTCK
feature. Not all dongles support this - keep reading!
The RTCK signal often found in some ARM chips is used to help with
this problem. ARM has a good description of the problem described at
this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
-28/nov/2008]. Link title: ``How does the jtag synchronisation logic
-work? / how does adaptive clocking working?''.
+28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
+work? / how does adaptive clocking work?''.
The nice thing about adaptive clocking is that ``battery powered hand
held device example'' - the adaptiveness works perfectly all the
time. One can set a break point or halt the system in the deep power
down code, slow step out until the system speeds up.
-@b{Solution #2 - Always works - but is slower}
+@b{Solution #2 - Always works - but may be slower}
Often this is a perfectly acceptable solution.
-In the most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
-the target clock speed. But what is that ``magic division'' it varies
-depending upon the chips on your board. @b{ARM Rule of thumb} Most ARM
-based systems require an 8:1 division. @b{Xilinx Rule of thumb} is
+In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
+the target clock speed. But what that ``magic division'' is varies
+depending on the chips on your board. @b{ARM rule of thumb} Most ARM
+based systems require an 8:1 division. @b{Xilinx rule of thumb} is
1/12 the clock speed.
-Note: Many FTDI2232C based JTAG dongles are limited to 6mhz.
+Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
-You can still debug the 'lower power' situations - you just need to
+You can still debug the 'low power' situations - you just need to
manually adjust the clock speed at every step. While painful and
-teadious, it is not always practical.
+tedious, it is not always practical.
-It is however easy to ``code your way around it'' - ie: Cheat a little
+It is however easy to ``code your way around it'' - i.e.: Cheat a little,
have a special debug mode in your application that does a ``high power
sleep''. If you are careful - 98% of your problems can be debugged
this way.
To set the JTAG frequency use the command:
@example
- # Example: 1.234mhz
+ # Example: 1.234MHz
jtag_khz 1234
@end example
-@item @b{Win32 Pathnames} Why does not backslashes in paths under Windows doesn't work?
+@item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
around Windows filenames.
@item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
Make sure you have Cygwin installed, or at least a version of OpenOCD that
-claims to come with all the necessary dlls. When using Cygwin, try launching
+claims to come with all the necessary DLLs. When using Cygwin, try launching
OpenOCD from the Cygwin shell.
@item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
GDB issues software breakpoints when a normal breakpoint is requested, or to implement
-source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
+source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
software breakpoints consume one of the two available hardware breakpoints.
-@item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
-and works sometimes fine.
+@item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
Make sure the core frequency specified in the @option{flash lpc2000} line matches the
clock at the time you're programming the flash. If you've specified the crystal's
-frequency, make sure the PLL is disabled, if you've specified the full core speed
+frequency, make sure the PLL is disabled. If you've specified the full core speed
(e.g. 60MHz), make sure the PLL is enabled.
@item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
a proper "initial" stack frame, if you happen to know what exactly has to
be done, feel free to add this here.
-@b{Simple:} In your startup code - push 8 registers of ZEROs onto the
+@b{Simple:} In your startup code - push 8 registers of zeros onto the
stack before calling main(). What GDB is doing is ``climbing'' the run
time stack by reading various values on the stack using the standard
call frame for the target. GDB keeps going - until one of 2 things
happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
-stackframes have been processed. By pushing ZEROs on the stack, GDB
+stackframes have been processed. By pushing zeros on the stack, GDB
gracefully stops.
@b{Debugging Interrupt Service Routines} - In your ISR before you call
-your C code, do the same, artifically push some zeros on to the stack,
+your C code, do the same - artifically push some zeros onto the stack,
remember to pop them off when the ISR is done.
@b{Also note:} If you have a multi-threaded operating system, they
reset, everything else should work fine.
@item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
-Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
+toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
unstable. When single-stepping over large blocks of code, GDB and OpenOCD
quit with an error message. Is there a stability issue with OpenOCD?
You can use the ``scan_chain'' command to verify and display the tap order.
-@item @b{JTAG Tap Order} JTAG Tap Order - Command Order
+Also, some commands can't execute until after @command{init} has been
+processed. Such commands include @command{nand probe} and everything
+else that needs to write to controller registers, perhaps for setting
+up DRAM and loading it with code.
+
+@item @b{JTAG Tap Order} JTAG tap order - command order
Many newer devices have multiple JTAG taps. For example: ST
Microsystems STM32 chips have two taps, a ``boundary scan tap'' and
-``cortexM3'' tap. Example: The STM32 reference manual, Document ID:
+``Cortex-M3'' tap. Example: The STM32 reference manual, Document ID:
RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
-connected to the Boundary Scan Tap, which then connects to the
-CortexM3 Tap, which then connects to the TDO pin.
+connected to the boundary scan tap, which then connects to the
+Cortex-M3 tap, which then connects to the TDO pin.
-Thus, the proper order for the STM32 chip is: (1) The CortexM3, then
-(2) The Boundary Scan Tap. If your board includes an additional JTAG
+Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
+(2) The boundary scan tap. If your board includes an additional JTAG
chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
-place it before or after the stm32 chip in the chain. For example:
+place it before or after the STM32 chip in the chain. For example:
@itemize @bullet
@item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
-@item STM32 BS TDO (output) -> STM32 CortexM3 TDI (input)
-@item STM32 CortexM3 TDO (output) -> SM32 TDO Pin
+@item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
+@item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
@item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
@item Xilinx TDO Pin -> OpenOCD TDO (input)
@end itemize
-The ``jtag device'' commands would thus be in the order shown below. Note
+The ``jtag device'' commands would thus be in the order shown below. Note:
@itemize @bullet
@item jtag newtap Xilinx tap -irlen ...
@end enumerate
-@node TCL Crash Course
-@chapter TCL Crash Course
-@cindex TCL
+@node Tcl Crash Course
+@chapter Tcl Crash Course
+@cindex Tcl
-Not everyone knows TCL - this is not intended to be a replacement for
-learning TCL, the intent of this chapter is to give you some idea of
-how the TCL Scripts work.
+Not everyone knows Tcl - this is not intended to be a replacement for
+learning Tcl, the intent of this chapter is to give you some idea of
+how the Tcl scripts work.
This chapter is written with two audiences in mind. (1) OpenOCD users
who need to understand a bit more of how JIM-Tcl works so they can do
something useful, and (2) those that want to add a new command to
OpenOCD.
-@section TCL Rule #1
+@section Tcl Rule #1
There is a famous joke, it goes like this:
@enumerate
@item Rule #1: The wife is always correct
@item Rule #2: If you think otherwise, See Rule #1
@end enumerate
-The TCL equal is this:
+The Tcl equal is this:
@enumerate
@item Rule #1: Everything is a string
@end enumerate
As in the famous joke, the consequences of Rule #1 are profound. Once
-you understand Rule #1, you will understand TCL.
+you understand Rule #1, you will understand Tcl.
-@section TCL Rule #1b
+@section Tcl Rule #1b
There is a second pair of rules.
@enumerate
@item Rule #1: Control flow does not exist. Only commands
@* For example: the classic FOR loop or IF statement is not a control
flow item, they are commands, there is no such thing as control flow
-in TCL.
+in Tcl.
@item Rule #2: If you think otherwise, See Rule #1
@* Actually what happens is this: There are commands that by
convention, act like control flow key words in other languages. One of
@end enumerate
@section Per Rule #1 - All Results are strings
-Every TCL command results in a string. The word ``result'' is used
+Every Tcl command results in a string. The word ``result'' is used
deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
Everything is a string}
-@section TCL Quoting Operators
-In life of a TCL script, there are two important periods of time, the
+@section Tcl Quoting Operators
+In life of a Tcl script, there are two important periods of time, the
difference is subtle.
@enumerate
@item Parse Time
@item Evaluation Time
@end enumerate
-The two key items here are how ``quoted things'' work in TCL. TCL has
+The two key items here are how ``quoted things'' work in Tcl. Tcl has
three primary quoting constructs, the [square-brackets] the
@{curly-braces@} and ``double-quotes''
By now you should know $VARIABLES always start with a $DOLLAR
-sign. BTW, to set a variable, you actually use the command ``set'', as
+sign. BTW: To set a variable, you actually use the command ``set'', as
in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
= 1'' statement, but without the equal sign.
@itemize @bullet
@item @b{[square-brackets]}
-@* @b{[square-brackets]} are command subsitution. It operates much
+@* @b{[square-brackets]} are command substitutions. It operates much
like Unix Shell `back-ticks`. The result of a [square-bracket]
operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
-string}. These two statments are roughly identical.
+string}. These two statements are roughly identical:
@example
# bash example
X=`date`
echo "The Date is: $X"
- # TCL example
+ # Tcl example
set X [date]
puts "The Date is: $X"
@end example
@*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
'single-quote' operators in BASH shell scripts, with the added
-feature: @{curly-braces@} nest, single quotes can not. @{@{@{this is
+feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
28/nov/2008, Jim/OpenOCD does not have a date command.
@end itemize
@section Consequences of Rule 1/2/3/4
-The consequences of Rule 1 is profound.
+The consequences of Rule 1 are profound.
-@subsection Tokenizing & Execution.
+@subsection Tokenisation & Execution.
Of course, whitespace, blank lines and #comment lines are handled in
the normal way.
As a script is parsed, each (multi) line in the script file is
-tokenized and according to the quoting rules. After tokenizing, that
+tokenised and according to the quoting rules. After tokenisation, that
line is immedatly executed.
Multi line statements end with one or more ``still-open''
-@{curly-braces@} which - eventually - a few lines later closes.
+@{curly-braces@} which - eventually - closes a few lines later.
@subsection Command Execution
-Remember earlier: There is no such thing as ``control flow''
-statements in TCL. Instead there are COMMANDS that simpily act like
+Remember earlier: There are no ``control flow''
+statements in Tcl. Instead there are COMMANDS that simply act like
control flow operators.
Commands are executed like this:
command stores these items in a table somewhere so it can be found by
``LookupCommand()''
-@subsection The FOR Command
+@subsection The FOR command
-The most interesting command to look at is the FOR command. In TCL,
-the FOR command is normally implimented in C. Remember, FOR is a
+The most interesting command to look at is the FOR command. In Tcl,
+the FOR command is normally implemented in C. Remember, FOR is a
command just like any other command.
When the ascii text containing the FOR command is parsed, the parser
Often many of those parameters are in @{curly-braces@} - thus the
variables inside are not expanded or replaced until later.
-Remember that every TCL command looks like the classic ``main( argc,
+Remember that every Tcl command looks like the classic ``main( argc,
argv )'' function in C. In JimTCL - they actually look like this:
@example
Jim_Obj * const *argvs );
@end example
-Real TCL is nearly identical. Although the newer versions have
+Real Tcl is nearly identical. Although the newer versions have
introduced a byte-code parser and intepreter, but at the core, it
still operates in the same basic way.
-@subsection FOR Command Implimentation
+@subsection FOR command implementation
-To understand TCL it is perhaps most helpful to see the FOR
+To understand Tcl it is perhaps most helpful to see the FOR
command. Remember, it is a COMMAND not a control flow structure.
-In TCL there are two underying C helper functions.
+In Tcl there are two underlying C helper functions.
Remember Rule #1 - You are a string.
The @b{first} helper parses and executes commands found in an ascii
-string. Commands can be seperated by semi-colons, or newlines. While
-parsing, variables are expanded per the quoting rules
+string. Commands can be seperated by semicolons, or newlines. While
+parsing, variables are expanded via the quoting rules.
The @b{second} helper evaluates an ascii string as a numerical
expression and returns a value.
Here is an example of how the @b{FOR} command could be
-implimented. The pseudo code below does not show error handling.
+implemented. The pseudo code below does not show error handling.
@example
void Execute_AsciiString( void *interp, const char *string );
Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
in the same basic way.
-@section OpenOCD TCL Usage
+@section OpenOCD Tcl Usage
@subsection source and find commands
@b{Where:} In many configuration files
@item The FIND command is in square brackets.
@* The FIND command is executed with the parameter FILENAME. It should
find the full path to the named file. The RESULT is a string, which is
-subsituted on the orginal command line.
+substituted on the orginal command line.
@item The command source is executed with the resulting filename.
@* SOURCE reads a file and executes as a script.
@end enumerate
@subsection format command
@b{Where:} Generally occurs in numerous places.
-@* TCL no command like @b{printf()}, intead it has @b{format}, which is really more like
-@b{sprintf()}.
+@* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
+@b{sprintf()}.
@b{Example}
@example
set x 6
@* Refer to Rule #1.
@item The PUTS command outputs the text.
@end enumerate
-@subsection Body Or Inlined Text
+@subsection Body or Inlined Text
@b{Where:} Various TARGET scripts.
@example
#1 Good
@*There are 4 examples:
@enumerate
@item The TCLBODY is a simple string that happens to be a proc name
-@item The TCLBODY is several simple commands semi-colon seperated
+@item The TCLBODY is several simple commands seperated by semicolons
@item The TCLBODY is a multi-line @{curly-brace@} quoted string
@item The TCLBODY is a string with variables that get expanded.
@end enumerate
@subsection Global Variables
@b{Where:} You might discover this when writing your own procs @* In
simple terms: Inside a PROC, if you need to access a global variable
-you must say so. Also see ``upvar''. Example:
+you must say so. See also ``upvar''. Example:
@example
proc myproc @{ @} @{
set y 0 #Local variable Y
@}
@end example
@section Other Tcl Hacks
-@b{Dynamic Variable Creation}
+@b{Dynamic variable creation}
@example
# Dynamically create a bunch of variables.
for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
set $vn [expr (1 << $x)]
@}
@end example
-@b{Dynamic Proc/Command Creation}
+@b{Dynamic proc/command creation}
@example
# One "X" function - 5 uart functions.
foreach who @{A B C D E@}
@}
@end example
-@node Target library
-@chapter Target library
-@cindex Target library
+@node Target Library
+@chapter Target Library
+@cindex Target Library
OpenOCD comes with a target configuration script library. These scripts can be
used as-is or serve as a starting point.
the path to the target library is in the OpenOCD script search path.
Similarly there are example scripts for configuring the JTAG interface.
-The command line below uses the example parport configuration scripts
+The command line below uses the example parport configuration script
that ship with OpenOCD, then configures the str710.cfg target and
-finally issues the init and reset command. The communication speed
+finally issues the init and reset commands. The communication speed
is set to 10kHz for reset and 8MHz for post reset.
-
@example
openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
@end example
-
To list the target scripts available:
@example
at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
@end example
-
-
@include fdl.texi
-@node OpenOCD Index
+@node OpenOCD Concept Index
@comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
@comment case issue with ``Index.html'' and ``index.html''
@comment Occurs when creating ``--html --no-split'' output
@comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
-@unnumbered OpenOCD Index
+@unnumbered OpenOCD Concept Index
@printindex cp
+@node OpenOCD Command Index
+@unnumbered OpenOCD Command Index
+@printindex fn
+
@bye
Code Review / openocd.git / blobdiff