under the terms of the GNU Free Documentation License, Version 1.2 or
any later version published by the Free Software Foundation; with no
Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
-Texts. A copy of the license is included in the section entitled ``GNU
+Texts. A copy of the license is included in the section entitled ``GNU
Free Documentation License''.
@end quotation
@end copying
* OpenOCD Project Setup:: OpenOCD Project Setup
* Config File Guidelines:: Config File Guidelines
* Daemon Configuration:: Daemon Configuration
-* Debug Adapter Configuration:: Debug Adapter Configuration
+* Debug Adapter Configuration:: Debug Adapter Configuration
* Reset Configuration:: Reset Configuration
* TAP Declaration:: TAP Declaration
* CPU Configuration:: CPU Configuration
* Flash Commands:: Flash Commands
-* NAND Flash Commands:: NAND Flash Commands
+* Flash Programming:: Flash Programming
* PLD/FPGA Commands:: PLD/FPGA Commands
* General Commands:: General Commands
* Architecture and Core Commands:: Architecture and Core Commands
* JTAG Commands:: JTAG Commands
* Boundary Scan Commands:: Boundary Scan Commands
+* Utility Commands:: Utility Commands
* TFTP:: TFTP
* GDB and OpenOCD:: Using GDB and OpenOCD
* Tcl Scripting API:: Tcl Scripting API
@unnumbered About
@cindex about
-OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
-University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
+OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
+at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
Since that time, the project has grown into an active open-source project,
supported by a diverse community of software and hardware developers from
around the world.
It does so with the assistance of a @dfn{debug adapter}, which is
a small hardware module which helps provide the right kind of
-electrical signaling to the target being debugged. These are
+electrical signaling to the target being debugged. These are
required since the debug host (on which OpenOCD runs) won't
usually have native support for such signaling, or the connector
needed to hook up to the target.
Such debug adapters support one or more @dfn{transport} protocols,
each of which involves different electrical signaling (and uses
-different messaging protocols on top of that signaling). There
+different messaging protocols on top of that signaling). There
are many types of debug adapter, and little uniformity in what
-they are called. (There are also product naming differences.)
+they are called. (There are also product naming differences.)
These adapters are sometimes packaged as discrete dongles, which
may generically be called @dfn{hardware interface dongles}.
Some development boards also integrate them directly, which may
-let the development board can be directly connected to the debug
+let the development board connect directly to the debug
host over USB (and sometimes also to power it over USB).
For example, a @dfn{JTAG Adapter} supports JTAG
signaling, and is used to communicate
with JTAG (IEEE 1149.1) compliant TAPs on your target board.
A @dfn{TAP} is a ``Test Access Port'', a module which processes
-special instructions and data. TAPs are daisy-chained within and
-between chips and boards. JTAG supports debugging and boundary
+special instructions and data. TAPs are daisy-chained within and
+between chips and boards. JTAG supports debugging and boundary
scan operations.
There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
signaling to communicate with some newer ARM cores, as well as debug
-adapters which support both JTAG and SWD transports. SWD only supports
+adapters which support both JTAG and SWD transports. SWD supports only
debugging, whereas JTAG also supports boundary scan operations.
For some chips, there are also @dfn{Programming Adapters} supporting
(At this writing, OpenOCD does not support such non-debug adapters.)
-@b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
-based, parallel port based, and other standalone boxes that run
+@b{Dongles:} OpenOCD currently supports many types of hardware dongles:
+USB-based, parallel port-based, and other standalone boxes that run
OpenOCD internally. @xref{Debug Adapter Hardware}.
@b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
-ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
-Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
-debugged via the GDB protocol.
+ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
+(Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
+based cores to be debugged via the GDB protocol.
-@b{Flash Programing:} Flash writing is supported for external CFI
-compatible NOR flashes (Intel and AMD/Spansion command set) and several
-internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
-STM32x). Preliminary support for various NAND flash controllers
-(LPC3180, Orion, S3C24xx, more) controller is included.
+@b{Flash Programming:} Flash writing is supported for external
+CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
+internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
+STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
+controllers (LPC3180, Orion, S3C24xx, more) is included.
@section OpenOCD Web Site
The OpenOCD web site provides the latest public news from the community:
-@uref{http://openocd.sourceforge.net/}
+@uref{http://openocd.org/}
@section Latest User's Guide:
The user's guide you are now reading may not be the latest one
-available. A version for more recent code may be available.
-Its HTML form is published irregularly at:
+available. A version for more recent code may be available.
+Its HTML form is published regularly at:
-@uref{http://openocd.sourceforge.net/doc/html/index.html}
+@uref{http://openocd.org/doc/html/index.html}
PDF form is likewise published at:
-@uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
+@uref{http://openocd.org/doc/pdf/openocd.pdf}
@section OpenOCD User's Forum
There is an OpenOCD forum (phpBB) hosted by SparkFun,
-which might be helpful to you. Note that if you want
+which might be helpful to you. Note that if you want
anything to come to the attention of developers, you
should post it to the OpenOCD Developer Mailing List
instead of this forum.
@uref{http://forum.sparkfun.com/viewforum.php?f=18}
+@section OpenOCD User's Mailing List
+
+The OpenOCD User Mailing List provides the primary means of
+communication between users:
+
+@uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
+
+@section OpenOCD IRC
+
+Support can also be found on irc:
+@uref{irc://irc.freenode.net/openocd}
@node Developers
@chapter OpenOCD Developer Resources
@cindex developers
If you are interested in improving the state of OpenOCD's debugging and
-testing support, new contributions will be welcome. Motivated developers
+testing support, new contributions will be welcome. Motivated developers
can produce new target, flash or interface drivers, improve the
documentation, as well as more conventional bug fixes and enhancements.
The resources in this chapter are available for developers wishing to explore
or expand the OpenOCD source code.
-@section OpenOCD GIT Repository
+@section OpenOCD Git Repository
During the 0.3.x release cycle, OpenOCD switched from Subversion to
-a GIT repository hosted at SourceForge. The repository URL is:
+a Git repository hosted at SourceForge. The repository URL is:
-@uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
+@uref{git://git.code.sf.net/p/openocd/code}
+
+or via http
+
+@uref{http://git.code.sf.net/p/openocd/code}
You may prefer to use a mirror and the HTTP protocol:
@uref{http://repo.or.cz/r/openocd.git}
-With standard GIT tools, use @command{git clone} to initialize
+With standard Git tools, use @command{git clone} to initialize
a local repository, and @command{git pull} to update it.
There are also gitweb pages letting you browse the repository
with a web browser, or download arbitrary snapshots without
-needing a GIT client:
-
-@uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
+needing a Git client:
@uref{http://repo.or.cz/w/openocd.git}
@section Doxygen Developer Manual
During the 0.2.x release cycle, the OpenOCD project began
-providing a Doxygen reference manual. This document contains more
+providing a Doxygen reference manual. This document contains more
technical information about the software internals, development
processes, and similar documentation:
-@uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
+@uref{http://openocd.org/doc/doxygen/html/index.html}
This document is a work-in-progress, but contributions would be welcome
-to fill in the gaps. All of the source files are provided in-tree,
-listed in the Doxyfile configuration in the top of the source tree.
+to fill in the gaps. All of the source files are provided in-tree,
+listed in the Doxyfile configuration at the top of the source tree.
+
+@section Gerrit Review System
+
+All changes in the OpenOCD Git repository go through the web-based Gerrit
+Code Review System:
+
+@uref{http://openocd.zylin.com/}
+
+After a one-time registration and repository setup, anyone can push commits
+from their local Git repository directly into Gerrit.
+All users and developers are encouraged to review, test, discuss and vote
+for changes in Gerrit. The feedback provides the basis for a maintainer to
+eventually submit the change to the main Git repository.
+
+The @file{HACKING} file, also available as the Patch Guide in the Doxygen
+Developer Manual, contains basic information about how to connect a
+repository to Gerrit, prepare and push patches. Patch authors are expected to
+maintain their changes while they're in Gerrit, respond to feedback and if
+necessary rework and push improved versions of the change.
@section OpenOCD Developer Mailing List
@uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
-Discuss and submit patches to this list.
-The @file{HACKING} file contains basic information about how
-to prepare patches.
+@section OpenOCD Bug Tracker
-@section OpenOCD Bug Database
+The OpenOCD Bug Tracker is hosted on SourceForge:
-During the 0.4.x release cycle the OpenOCD project team began
-using Trac for its bug database:
-
-@uref{https://sourceforge.net/apps/trac/openocd}
+@uref{http://bugs.openocd.org/}
@node Debug Adapter Hardware
@cindex USB Adapter
@cindex RTCK
-Defined: @b{dongle}: A small device that plugins into a computer and serves as
+Defined: @b{dongle}: A small device that plugs into a computer and serves as
an adapter .... [snip]
In the OpenOCD case, this generally refers to @b{a small adapter} that
-attaches to your computer via USB or the Parallel Printer Port. One
-exception is the Zylin ZY1000, packaged as a small box you attach via
-an ethernet cable. The Zylin ZY1000 has the advantage that it does not
+attaches to your computer via USB or the parallel port. One
+exception is the Ultimate Solutions ZY1000, packaged as a small box you
+attach via an ethernet cable. The ZY1000 has the advantage that it does not
require any drivers to be installed on the developer PC. It also has
a built in web interface. It supports RTCK/RCLK or adaptive clocking
-and has a built in relay to power cycle targets remotely.
+and has a built-in relay to power cycle targets remotely.
@section Choosing a Dongle
@enumerate
@item @b{Transport} Does it support the kind of communication that you need?
-OpenOCD focusses mostly on JTAG. Your version may also support
+OpenOCD focusses mostly on JTAG. Your version may also support
other ways to communicate with target devices.
@item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
-Does your dongle support it? You might need a level converter.
+Does your dongle support it? You might need a level converter.
@item @b{Pinout} What pinout does your target board use?
-Does your dongle support it? You may be able to use jumper
+Does your dongle support it? You may be able to use jumper
wires, or an "octopus" connector, to convert pinouts.
-@item @b{Connection} Does your computer have the USB, printer, or
+@item @b{Connection} Does your computer have the USB, parallel, or
Ethernet port needed?
@item @b{RTCK} Do you expect to use it with ARM chips and boards with
-RTCK support? Also known as ``adaptive clocking''
+RTCK support (also known as ``adaptive clocking'')?
@end enumerate
-@section Stand alone Systems
+@section Stand-alone JTAG Probe
-@b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe} Technically, not a
-dongle, but a standalone box. The ZY1000 has the advantage that it does
-not require any drivers installed on the developer PC. It also has
-a built in web interface. It supports RTCK/RCLK or adaptive clocking
-and has a built in relay to power cycle targets remotely.
+The ZY1000 from Ultimate Solutions is technically not a dongle but a
+stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
+running on the developer's host computer.
+Once installed on a network using DHCP or a static IP assignment, users can
+access the ZY1000 probe locally or remotely from any host with access to the
+IP address assigned to the probe.
+The ZY1000 provides an intuitive web interface with direct access to the
+OpenOCD debugger.
+Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
+of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
+the target.
+The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
+to power cycle the target remotely.
+
+For more information, visit:
+
+@b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
@section USB FT2232 Based
-There are many USB JTAG dongles on the market, many of them are based
+There are many USB JTAG dongles on the market, many of them based
on a chip from ``Future Technology Devices International'' (FTDI)
known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
See: @url{http://www.ftdichip.com} for more information.
In summer 2009, USB high speed (480 Mbps) versions of these FTDI
-chips are starting to become available in JTAG adapters. (Adapters
-using those high speed FT2232H chips may support adaptive clocking.)
+chips started to become available in JTAG adapters. Around 2012, a new
+variant appeared - FT232H - this is a single-channel version of FT2232H.
+(Adapters using those high speed FT2232H or FT232H chips may support adaptive
+clocking.)
The FT2232 chips are flexible enough to support some other
transport options, such as SWD or the SPI variants used to
other one is used to provide a debug adapter.
Also, some development boards integrate an FT2232 chip to serve as
-a built-in low cost debug adapter and usb-to-serial solution.
+a built-in low-cost debug adapter and USB-to-serial solution.
@itemize @bullet
@item @b{usbjtag}
@item @b{signalyzer}
@* See: @url{http://www.signalyzer.com}
@item @b{Stellaris Eval Boards}
-@* See: @url{http://www.luminarymicro.com} - The Stellaris eval boards
+@* See: @url{http://www.ti.com} - The Stellaris eval boards
bundle FT2232-based JTAG and SWD support, which can be used to debug
-the Stellaris chips. Using separate JTAG adapters is optional.
+the Stellaris chips. Using separate JTAG adapters is optional.
These boards can also be used in a "pass through" mode as JTAG adapters
to other target boards, disabling the Stellaris chip.
-@item @b{Luminary ICDI}
-@* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug
+@item @b{TI/Luminary ICDI}
+@* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
Interface (ICDI) Boards are included in Stellaris LM3S9B9x
-Evaluation Kits. Like the non-detachable FT2232 support on the other
+Evaluation Kits. Like the non-detachable FT2232 support on the other
Stellaris eval boards, they can be used to debug other target boards.
@item @b{olimex-jtag}
@* See: @url{http://www.olimex.com}
@item @b{stm32stick}
@* Link @url{http://www.hitex.com/stm32-stick}
@item @b{axm0432_jtag}
-@* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
+@* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
to be available anymore as of April 2012.
@item @b{cortino}
@* Link @url{http://www.hitex.com/index.php?id=cortino}
@* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
@item @b{digilent-hs1}
@* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
-@end itemize
+@item @b{opendous}
+@* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
+(OpenHardware).
+@item @b{JTAG-lock-pick Tiny 2}
+@* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
+@item @b{GW16042}
+@* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
+FT2232H-based
+
+@end itemize
@section USB-JTAG / Altera USB-Blaster compatibles
These devices also show up as FTDI devices, but are not
protocol-compatible with the FT2232 devices. They are, however,
-protocol-compatible among themselves. USB-JTAG devices typically consist
+protocol-compatible among themselves. USB-JTAG devices typically consist
of a FT245 followed by a CPLD that understands a particular protocol,
-or emulate this protocol using some other hardware.
+or emulates this protocol using some other hardware.
They may appear under different USB VID/PID depending on the particular
-product. The driver can be configured to search for any VID/PID pair
+product. The driver can be configured to search for any VID/PID pair
(see the section on driver commands).
@itemize
@end itemize
@section USB RLINK based
-Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
+Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
+permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
+SWD and not JTAG, thus not supported.
@itemize @bullet
@item @b{Raisonance RLink}
-@* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
+@* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
@item @b{STM32 Primer}
@* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
@item @b{STM32 Primer2}
@* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
@end itemize
-For info the original ST-LINK enumerates using the mass storage usb class, however
-it's implementation is completely broken. The result is this causes issues under linux.
-The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
+For info the original ST-LINK enumerates using the mass storage usb class; however,
+its implementation is completely broken. The result is this causes issues under Linux.
+The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
@itemize @bullet
@item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
@item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
@end itemize
+@section USB TI/Stellaris ICDI based
+Texas Instruments has an adapter called @b{ICDI}.
+It is not to be confused with the FTDI based adapters that were originally fitted to their
+evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
+
+@section USB CMSIS-DAP based
+ARM has released a interface standard called CMSIS-DAP that simplifies connecting
+debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
+
@section USB Other
@itemize @bullet
@item @b{USBprog}
@* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
@item @b{opendous}
-@* Link: @url{http://code.google.com/p/opendous-jtag/}
+@* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
@item @b{estick}
@* Link: @url{http://code.google.com/p/estick-jtag/}
@section IBM PC Parallel Printer Port Based
-The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
+The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
and the Macraigor Wiggler. There are many clones and variations of
these on the market.
@item @b{Amontec - JTAG Accelerator}
@* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
-@item @b{GW16402}
-@* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
-
@item @b{Wiggler2}
@* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
@item @b{at91rm9200}
@* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
+@item @b{bcm2835gpio}
+@* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
+
+@item @b{jtag_vpi}
+@* A JTAG driver acting as a client for the JTAG VPI server interface.
+@* Link: @url{http://github.com/fjullien/jtag_vpi}
+
@end itemize
@node About Jim-Tcl
All commands presented in this Guide are extensions to Jim-Tcl.
You can use them as simple commands, without needing to learn
much of anything about Tcl.
-Alternatively, can write Tcl programs with them.
+Alternatively, you can write Tcl programs with them.
-You can learn more about Jim at its website, @url{http://jim.berlios.de}.
+You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
There is an active and responsive community, get on the mailing list
if you have any questions. Jim-Tcl maintainers also lurk on the
OpenOCD mailing list.
@item @b{Scripts}
@* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
command interpreter today is a mixture of (newer)
-Jim-Tcl commands, and (older) the orginal command interpreter.
+Jim-Tcl commands, and the (older) original command interpreter.
@item @b{Commands}
@* At the OpenOCD telnet command line (or via the GDB monitor command) one
@item @b{Historical Note}
@* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
-before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
-as a git submodule, which greatly simplified upgrading Jim Tcl
-to benefit from new features and bugfixes in Jim Tcl.
+before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
+as a Git submodule, which greatly simplified upgrading Jim-Tcl
+to benefit from new features and bugfixes in Jim-Tcl.
@item @b{Need a crash course in Tcl?}
@*@xref{Tcl Crash Course}.
@cindex directory search
Properly installing OpenOCD sets up your operating system to grant it access
-to the debug adapters. On Linux, this usually involves installing a file
-in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
-complex and confusing driver configuration for every peripheral. Such issues
+to the debug adapters. On Linux, this usually involves installing a file
+in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
+that works for many common adapters is shipped with OpenOCD in the
+@file{contrib} directory. MS-Windows needs
+complex and confusing driver configuration for every peripheral. Such issues
are unique to each operating system, and are not detailed in this User's Guide.
Then later you will invoke the OpenOCD server, with various options to
@quotation Note
Don't try to use configuration script names or paths which
-include the "#" character. That character begins Tcl comments.
+include the "#" character. That character begins Tcl comments.
@end quotation
@section Simple setup, no customization
In the best case, you can use two scripts from one of the script
libraries, hook up your JTAG adapter, and start the server ... and
-your JTAG setup will just work "out of the box". Always try to
+your JTAG setup will just work "out of the box". Always try to
start by reusing those scripts, but assume you'll need more
-customization even if this works. @xref{OpenOCD Project Setup}.
+customization even if this works. @xref{OpenOCD Project Setup}.
If you find a script for your JTAG adapter, and for your board or
target, you may be able to hook up your JTAG adapter then start
-the server like:
+the server with some variation of one of the following:
@example
openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
+openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
@end example
You might also need to configure which reset signals are present,
@example
Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
For bug reports, read
- http://openocd.sourceforge.net/doc/doxygen/bugs.html
+ http://openocd.org/doc/doxygen/bugs.html
Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
(mfg: 0x23b, part: 0xba00, ver: 0x3)
@end example
Seeing that "tap/device found" message, and no warnings, means
-the JTAG communication is working. That's a key milestone, but
+the JTAG communication is working. That's a key milestone, but
you'll probably need more project-specific setup.
@section What OpenOCD does as it starts
OpenOCD starts by processing the configuration commands provided
on the command line or, if there were no @option{-c command} or
@option{-f file.cfg} options given, in @file{openocd.cfg}.
-@xref{Configuration Stage}.
+@xref{configurationstage,,Configuration Stage}.
At the end of the configuration stage it verifies the JTAG scan
chain defined using those commands; your configuration should
ensure that this always succeeds.
@option{debug_level} to "3", outputting the most information,
including debug messages. The default setting is "2", outputting only
informational messages, warnings and errors. You can also change this
-setting from within a telnet or gdb session using @command{debug_level
-<n>} (@pxref{debug_level}).
+setting from within a telnet or gdb session using @command{debug_level<n>}
+(@pxref{debuglevel,,debug_level}).
You can redirect all output from the daemon to a file using the
@option{-l <logfile>} switch.
@chapter OpenOCD Project Setup
To use OpenOCD with your development projects, you need to do more than
-just connecting the JTAG adapter hardware (dongle) to your development board
-and then starting the OpenOCD server.
-You also need to configure that server so that it knows
-about that adapter and board, and helps your work.
+just connect the JTAG adapter hardware (dongle) to your development board
+and start the OpenOCD server.
+You also need to configure your OpenOCD server so that it knows
+about your adapter and board, and helps your work.
You may also want to connect OpenOCD to GDB, possibly
using Eclipse or some other GUI.
with 1.2 Volt boards.
@item @emph{Be certain the cable is properly oriented} or you might
-damage your board. In most cases there are only two possible
+damage your board. In most cases there are only two possible
ways to connect the cable.
Connect the JTAG cable from your adapter to the board.
Be sure it's firmly connected.
If there's no housing, then you must look carefully and
make sure pin 1 on the cable hooks up to pin 1 on the board.
Ribbon cables are frequently all grey except for a wire on one
-edge, which is red. The red wire is pin 1.
+edge, which is red. The red wire is pin 1.
Sometimes dongles provide cables where one end is an ``octopus'' of
color coded single-wire connectors, instead of a connector block.
you are using to run OpenOCD.
For Ethernet, consult the documentation and your network administrator.
-For USB based JTAG adapters you have an easy sanity check at this point:
-does the host operating system see the JTAG adapter? If that host is an
+For USB-based JTAG adapters you have an easy sanity check at this point:
+does the host operating system see the JTAG adapter? If you're running
+Linux, try the @command{lsusb} command. If that host is an
MS-Windows host, you'll need to install a driver before OpenOCD works.
@item @emph{Connect the adapter's power supply, if needed.}
that can be tested in a later script.
@end quotation
-Here we will focus on the simpler solution: one user config
+Here we will focus on the simpler solution: one user config
file, including basic configuration plus any TCL procedures
to simplify your work.
(probably in @file{/usr/share/openocd/scripts} on Linux).
Board and tool vendors can provide these too, as can individual
user sites; the @option{-s} command line option lets you say
-where to find these files. (@xref{Running}.)
+where to find these files. (@xref{Running}.)
The AT91SAM7X256 example above works this way.
Three main types of non-user configuration file each have their
@item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
@end enumerate
-Best case: include just two files, and they handle everything else.
+Best case: include just two files, and they handle everything else.
The first is an interface config file.
The second is board-specific, and it sets up the JTAG TAPs and
their GDB targets (by deferring to some @file{target.cfg} file),
Once you find the JTAG TAPs, you can just search for appropriate
target and board
configuration files ... or write your own, from the bottom up.
-@xref{Autoprobing}.
+@xref{autoprobing,,Autoprobing}.
@item You can often reuse some standard config files but
need to write a few new ones, probably a @file{board.cfg} file.
@item
You may may need to write some C code.
-It may be as simple as a supporting a new ft2232 or parport
+It may be as simple as supporting a new FT2232 or parport
based adapter; a bit more involved, like a NAND or NOR flash
controller driver; or a big piece of work like supporting
a new chip architecture.
Likewise, the @command{arm9 vector_catch} command (or
@cindex vector_catch
its siblings @command{xscale vector_catch}
-and @command{cortex_m3 vector_catch}) can be a timesaver
+and @command{cortex_m vector_catch}) can be a timesaver
during some debug sessions, but don't make everyone use that either.
Keep those kinds of debugging aids in your user config file,
along with messaging and tracing setup.
-(@xref{Software Debug Messages and Tracing}.)
+(@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
@item
You might need to override some defaults.
@item
TCP/IP port configuration is another example of something which
is environment-specific, and should only appear in
-a user config file. @xref{TCP/IP Ports}.
+a user config file. @xref{tcpipports,,TCP/IP Ports}.
@end itemize
@section Project-Specific Utilities
@example
proc newboot @{ @} @{
- # Reset, leaving the CPU halted. The "reset-init" event
+ # Reset, leaving the CPU halted. The "reset-init" event
# proc gives faster access to the CPU and to NOR flash;
# "reset halt" would be slower.
reset init
@item @b{Watchdog Timers}...
Watchog timers are typically used to automatically reset systems if
-some application task doesn't periodically reset the timer. (The
+some application task doesn't periodically reset the timer. (The
assumption is that the system has locked up if the task can't run.)
When a JTAG debugger halts the system, that task won't be able to run
and reset the timer ... potentially causing resets in the middle of
That might however be your only option.
Look instead for chip-specific ways to stop the watchdog from counting
-while the system is in a debug halt state. It may be simplest to set
-that non-counting mode in your debugger startup scripts. You may however
+while the system is in a debug halt state. It may be simplest to set
+that non-counting mode in your debugger startup scripts. You may however
need a different approach when, for example, a motor could be physically
-damaged by firmware remaining inactive in a debug halt state. That might
+damaged by firmware remaining inactive in a debug halt state. That might
involve a type of firmware mode where that "non-counting" mode is disabled
at the beginning then re-enabled at the end; a watchdog reset might fire
and complicate the debug session, but hardware (or people) would be
protected.@footnote{Note that many systems support a "monitor mode" debug
-that is a somewhat cleaner way to address such issues. You can think of
+that is a somewhat cleaner way to address such issues. You can think of
it as only halting part of the system, maybe just one task,
instead of the whole thing.
At this writing, January 2010, OpenOCD based debugging does not support
@uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
The CodeSourcery EABI toolchain also includes a semihosting library.},
-your target code can use I/O facilities on the debug host. That library
+your target code can use I/O facilities on the debug host. That library
provides a small set of system calls which are handled by OpenOCD.
It can let the debugger provide your system console and a file system,
helping with early debugging or providing a more capable environment
over JTAG, by @emph{linking with a small library of code}
provided with OpenOCD and using the utilities there to send
various kinds of message.
-@xref{Software Debug Messages and Tracing}.
+@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
@end itemize
Chip vendors often provide software development boards which
are highly configurable, so that they can support all options
-that product boards may require. @emph{Make sure that any
+that product boards may require. @emph{Make sure that any
jumpers or switches match the system configuration you are
working with.}
@item @b{Boot Modes} ...
Complex chips often support multiple boot modes, controlled
-by external jumpers. Make sure this is set up correctly.
+by external jumpers. Make sure this is set up correctly.
For example many i.MX boards from NXP need to be jumpered
to "ATX mode" to start booting using the on-chip ROM, when
using second stage bootloader code stored in a NAND flash chip.
Such explicit configuration is common, and not limited to
-booting from NAND. You might also need to set jumpers to
+booting from NAND. You might also need to set jumpers to
start booting using code loaded from an MMC/SD card; external
SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
flash; some external host; or various other sources.
@item @b{Memory Addressing} ...
Boards which support multiple boot modes may also have jumpers
-to configure memory addressing. One board, for example, jumpers
+to configure memory addressing. One board, for example, jumpers
external chipselect 0 (used for booting) to address either
a large SRAM (which must be pre-loaded via JTAG), NOR flash,
-or NAND flash. When it's jumpered to address NAND flash, that
+or NAND flash. When it's jumpered to address NAND flash, that
board must also be told to start booting from on-chip ROM.
Your @file{board.cfg} file may also need to be told this jumper
@command{nand device}; and likewise which probe to perform in
its @code{reset-init} handler.
-A closely related issue is bus width. Jumpers might need to
+A closely related issue is bus width. Jumpers might need to
distinguish between 8 bit or 16 bit bus access for the flash
used to start booting.
This interacts with software
configuration of pin multiplexing, where for example a
given pin may be routed either to the MMC/SD controller
-or the GPIO controller. It also often interacts with
-configuration jumpers. One jumper may be used to route
+or the GPIO controller. It also often interacts with
+configuration jumpers. One jumper may be used to route
signals to an MMC/SD card slot or an expansion bus (which
might in turn affect booting); others might control which
audio or video codecs are used.
which set up the hardware to match that jumper configuration.
That includes in particular any oscillator or PLL used to clock
the CPU, and any memory controllers needed to access external
-memory and peripherals. Without such handlers, you won't be
+memory and peripherals. Without such handlers, you won't be
able to access those resources without working target firmware
which can do that setup ... this can be awkward when you're
-trying to debug that target firmware. Even if there's a ROM
+trying to debug that target firmware. Even if there's a ROM
bootloader which handles a few issues, it rarely provides full
access to all board-specific capabilities.
needs to get a new board working smoothly.
It provides guidelines for creating those files.
-You should find the following directories under @t{$(INSTALLDIR)/scripts},
-with files including the ones listed here.
-Use them as-is where you can; or as models for new files.
+You should find the following directories under
+@t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
+them as-is where you can; or as models for new files.
@itemize @bullet
@item @file{interface} ...
-These are for debug adapters.
-Files that configure JTAG adapters go here.
-@example
-$ ls interface
-altera-usb-blaster.cfg hilscher_nxhx50_etm.cfg openrd.cfg
-arm-jtag-ew.cfg hilscher_nxhx50_re.cfg osbdm.cfg
-arm-usb-ocd.cfg hitex_str9-comstick.cfg parport.cfg
-at91rm9200.cfg icebear.cfg parport_dlc5.cfg
-axm0432.cfg jlink.cfg redbee-econotag.cfg
-busblaster.cfg jtagkey2.cfg redbee-usb.cfg
-buspirate.cfg jtagkey2p.cfg rlink.cfg
-calao-usb-a9260-c01.cfg jtagkey.cfg sheevaplug.cfg
-calao-usb-a9260-c02.cfg jtagkey-tiny.cfg signalyzer.cfg
-calao-usb-a9260.cfg kt-link.cfg signalyzer-h2.cfg
-chameleon.cfg lisa-l.cfg signalyzer-h4.cfg
-cortino.cfg luminary.cfg signalyzer-lite.cfg
-digilent-hs1.cfg luminary-icdi.cfg stlink-v1.cfg
-dlp-usb1232h.cfg luminary-lm3s811.cfg stlink-v2.cfg
-dummy.cfg minimodule.cfg stm32-stick.cfg
-estick.cfg neodb.cfg turtelizer2.cfg
-flashlink.cfg ngxtech.cfg ulink.cfg
-flossjtag.cfg olimex-arm-usb-ocd.cfg usb-jtag.cfg
-flossjtag-noeeprom.cfg olimex-arm-usb-ocd-h.cfg usbprog.cfg
-flyswatter2.cfg olimex-arm-usb-tiny-h.cfg vpaclink.cfg
-flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
-hilscher_nxhx10_etm.cfg oocdlink.cfg xds100v2.cfg
-hilscher_nxhx500_etm.cfg opendous.cfg
-hilscher_nxhx500_re.cfg openocd-usb.cfg
-$
-@end example
+These are for debug adapters. Files that specify configuration to use
+specific JTAG, SWD and other adapters go here.
@item @file{board} ...
-think Circuit Board, PWA, PCB, they go by many names. Board files
+Think Circuit Board, PWA, PCB, they go by many names. Board files
contain initialization items that are specific to a board.
+
They reuse target configuration files, since the same
microprocessor chips are used on many boards,
-but support for external parts varies widely. For
+but support for external parts varies widely. For
example, the SDRAM initialization sequence for the board, or the type
-of external flash and what address it uses. Any initialization
+of external flash and what address it uses. Any initialization
sequence to enable that external flash or SDRAM should be found in the
-board file. Boards may also contain multiple targets: two CPUs; or
+board file. Boards may also contain multiple targets: two CPUs; or
a CPU and an FPGA.
-@example
-$ ls board
-actux3.cfg logicpd_imx27.cfg
-am3517evm.cfg lubbock.cfg
-arm_evaluator7t.cfg mcb1700.cfg
-at91cap7a-stk-sdram.cfg microchip_explorer16.cfg
-at91eb40a.cfg mini2440.cfg
-at91rm9200-dk.cfg mini6410.cfg
-at91rm9200-ek.cfg olimex_LPC2378STK.cfg
-at91sam9261-ek.cfg olimex_lpc_h2148.cfg
-at91sam9263-ek.cfg olimex_sam7_ex256.cfg
-at91sam9g20-ek.cfg olimex_sam9_l9260.cfg
-atmel_at91sam7s-ek.cfg olimex_stm32_h103.cfg
-atmel_at91sam9260-ek.cfg olimex_stm32_h107.cfg
-atmel_at91sam9rl-ek.cfg olimex_stm32_p107.cfg
-atmel_sam3n_ek.cfg omap2420_h4.cfg
-atmel_sam3s_ek.cfg open-bldc.cfg
-atmel_sam3u_ek.cfg openrd.cfg
-atmel_sam3x_ek.cfg osk5912.cfg
-atmel_sam4s_ek.cfg phytec_lpc3250.cfg
-balloon3-cpu.cfg pic-p32mx.cfg
-colibri.cfg propox_mmnet1001.cfg
-crossbow_tech_imote2.cfg pxa255_sst.cfg
-csb337.cfg redbee.cfg
-csb732.cfg rsc-w910.cfg
-da850evm.cfg sheevaplug.cfg
-digi_connectcore_wi-9c.cfg smdk6410.cfg
-diolan_lpc4350-db1.cfg spear300evb.cfg
-dm355evm.cfg spear300evb_mod.cfg
-dm365evm.cfg spear310evb20.cfg
-dm6446evm.cfg spear310evb20_mod.cfg
-efikamx.cfg spear320cpu.cfg
-eir.cfg spear320cpu_mod.cfg
-ek-lm3s1968.cfg steval_pcc010.cfg
-ek-lm3s3748.cfg stm320518_eval_stlink.cfg
-ek-lm3s6965.cfg stm32100b_eval.cfg
-ek-lm3s811.cfg stm3210b_eval.cfg
-ek-lm3s811-revb.cfg stm3210c_eval.cfg
-ek-lm3s9b9x.cfg stm3210e_eval.cfg
-ek-lm4f232.cfg stm3220g_eval.cfg
-embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
-ethernut3.cfg stm3241g_eval.cfg
-glyn_tonga2.cfg stm3241g_eval_stlink.cfg
-hammer.cfg stm32f0discovery.cfg
-hilscher_nxdb500sys.cfg stm32f4discovery.cfg
-hilscher_nxeb500hmi.cfg stm32ldiscovery.cfg
-hilscher_nxhx10.cfg stm32vldiscovery.cfg
-hilscher_nxhx500.cfg str910-eval.cfg
-hilscher_nxhx50.cfg telo.cfg
-hilscher_nxsb100.cfg ti_beagleboard.cfg
-hitex_lpc2929.cfg ti_beagleboard_xm.cfg
-hitex_stm32-performancestick.cfg ti_beaglebone.cfg
-hitex_str9-comstick.cfg ti_blaze.cfg
-iar_lpc1768.cfg ti_pandaboard.cfg
-iar_str912_sk.cfg ti_pandaboard_es.cfg
-icnova_imx53_sodimm.cfg topas910.cfg
-icnova_sam9g45_sodimm.cfg topasa900.cfg
-imx27ads.cfg twr-k60n512.cfg
-imx27lnst.cfg tx25_stk5.cfg
-imx28evk.cfg tx27_stk5.cfg
-imx31pdk.cfg unknown_at91sam9260.cfg
-imx35pdk.cfg uptech_2410.cfg
-imx53loco.cfg verdex.cfg
-keil_mcb1700.cfg voipac.cfg
-keil_mcb2140.cfg voltcraft_dso-3062c.cfg
-kwikstik.cfg x300t.cfg
-linksys_nslu2.cfg zy1000.cfg
-lisa-l.cfg
-$
-@end example
@item @file{target} ...
-think chip. The ``target'' directory represents the JTAG TAPs
+Think chip. The ``target'' directory represents the JTAG TAPs
on a chip
which OpenOCD should control, not a board. Two common types of targets
are ARM chips and FPGA or CPLD chips.
When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
the target config file defines all of them.
-@example
-$ ls target
-$duc702x.cfg ixp42x.cfg
-am335x.cfg k40.cfg
-amdm37x.cfg k60.cfg
-ar71xx.cfg lpc1768.cfg
-at32ap7000.cfg lpc2103.cfg
-at91r40008.cfg lpc2124.cfg
-at91rm9200.cfg lpc2129.cfg
-at91sam3ax_4x.cfg lpc2148.cfg
-at91sam3ax_8x.cfg lpc2294.cfg
-at91sam3ax_xx.cfg lpc2378.cfg
-at91sam3nXX.cfg lpc2460.cfg
-at91sam3sXX.cfg lpc2478.cfg
-at91sam3u1c.cfg lpc2900.cfg
-at91sam3u1e.cfg lpc2xxx.cfg
-at91sam3u2c.cfg lpc3131.cfg
-at91sam3u2e.cfg lpc3250.cfg
-at91sam3u4c.cfg lpc4350.cfg
-at91sam3u4e.cfg mc13224v.cfg
-at91sam3uxx.cfg nuc910.cfg
-at91sam3XXX.cfg omap2420.cfg
-at91sam4sXX.cfg omap3530.cfg
-at91sam4XXX.cfg omap4430.cfg
-at91sam7se512.cfg omap4460.cfg
-at91sam7sx.cfg omap5912.cfg
-at91sam7x256.cfg omapl138.cfg
-at91sam7x512.cfg pic32mx.cfg
-at91sam9260.cfg pxa255.cfg
-at91sam9260_ext_RAM_ext_flash.cfg pxa270.cfg
-at91sam9261.cfg pxa3xx.cfg
-at91sam9263.cfg readme.txt
-at91sam9.cfg samsung_s3c2410.cfg
-at91sam9g10.cfg samsung_s3c2440.cfg
-at91sam9g20.cfg samsung_s3c2450.cfg
-at91sam9g45.cfg samsung_s3c4510.cfg
-at91sam9rl.cfg samsung_s3c6410.cfg
-atmega128.cfg sharp_lh79532.cfg
-avr32.cfg smp8634.cfg
-c100.cfg spear3xx.cfg
-c100config.tcl stellaris.cfg
-c100helper.tcl stm32.cfg
-c100regs.tcl stm32f0x_stlink.cfg
-cs351x.cfg stm32f1x.cfg
-davinci.cfg stm32f1x_stlink.cfg
-dragonite.cfg stm32f2x.cfg
-dsp56321.cfg stm32f2x_stlink.cfg
-dsp568013.cfg stm32f2xxx.cfg
-dsp568037.cfg stm32f4x.cfg
-epc9301.cfg stm32f4x_stlink.cfg
-faux.cfg stm32l.cfg
-feroceon.cfg stm32lx_stlink.cfg
-fm3.cfg stm32_stlink.cfg
-hilscher_netx10.cfg stm32xl.cfg
-hilscher_netx500.cfg str710.cfg
-hilscher_netx50.cfg str730.cfg
-icepick.cfg str750.cfg
-imx21.cfg str912.cfg
-imx25.cfg swj-dp.tcl
-imx27.cfg test_reset_syntax_error.cfg
-imx28.cfg test_syntax_error.cfg
-imx31.cfg ti_dm355.cfg
-imx35.cfg ti_dm365.cfg
-imx51.cfg ti_dm6446.cfg
-imx53.cfg tmpa900.cfg
-imx.cfg tmpa910.cfg
-is5114.cfg u8500.cfg
-@end example
@item @emph{more} ... browse for other library files which may be useful.
For example, there are various generic and CPU-specific utilities.
@end itemize
In summary the board files should contain (if present)
@enumerate
-@item One or more @command{source [target/...cfg]} statements
-@item NOR flash configuration (@pxref{NOR Configuration})
-@item NAND flash configuration (@pxref{NAND Configuration})
+@item One or more @command{source [find target/...cfg]} statements
+@item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
+@item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
@item Target @code{reset} handlers for SDRAM and I/O configuration
@item JTAG adapter reset configuration (@pxref{Reset Configuration})
@item All things that are not ``inside a chip''
@end enumerate
Generic things inside target chips belong in target config files,
-not board config files. So for example a @code{reset-init} event
+not board config files. So for example a @code{reset-init} event
handler should know board-specific oscillator and PLL parameters,
which it passes to target-specific utility code.
or (assuming it needs it) load a configuration into the FPGA.
Such features are usually needed for low-level work with many boards,
where ``low level'' implies that the board initialization software may
-not be working. (That's a common reason to need JTAG tools. Another
+not be working. (That's a common reason to need JTAG tools. Another
is to enable working with microcontroller-based systems, which often
have no debugging support except a JTAG connector.)
Target config files may also export utility functions to board and user
-config files. Such functions should use name prefixes, to help avoid
+config files. Such functions should use name prefixes, to help avoid
naming collisions.
Board files could also accept input variables from user config files.
Except on microcontrollers, the basic job of @code{reset-init} event
handlers is setting up flash and DRAM, as normally handled by boot loaders.
Microcontrollers rarely use boot loaders; they run right out of their
-on-chip flash and SRAM memory. But they may want to use one of these
+on-chip flash and SRAM memory. But they may want to use one of these
handlers too, if just for developer convenience.
@quotation Note
Instead, look at the board config files distributed with OpenOCD.
If you have a boot loader, its source code will help; so will
configuration files for other JTAG tools
-(@pxref{Translating Configuration Files}).
+(@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
@end quotation
Some of this code could probably be shared between different boards.
(@emph{You might be that next person} trying to reuse init code!)
The last thing normally done in a @code{reset-init} handler is probing
-whatever flash memory was configured. For most chips that needs to be
+whatever flash memory was configured. For most chips that needs to be
done while the associated target is halted, either because JTAG memory
access uses the CPU or to prevent conflicting CPU access.
Before your @code{reset-init} handler has set up
the PLLs and clocking, you may need to run with
a low JTAG clock rate.
-@xref{JTAG Speed}.
+@xref{jtagspeed,,JTAG Speed}.
Then you'd increase that rate after your handler has
made it possible to use the faster JTAG clock.
When the initial low speed is board-specific, for example
If both the chip and the board support adaptive clocking,
use the @command{jtag_rclk}
command, in case your board is used with JTAG adapter which
-also supports it. Otherwise use @command{adapter_khz}.
+also supports it. Otherwise use @command{adapter_khz}.
Set the slow rate at the beginning of the reset sequence,
and the faster rate as soon as the clocks are at full speed.
-@anchor{The init_board procedure}
+@anchor{theinitboardprocedure}
@subsection The init_board procedure
@cindex init_board procedure
-The concept of @code{init_board} procedure is very similar to @code{init_targets} (@xref{The init_targets procedure}.)
-- it's a replacement of ``linear'' configuration scripts. This procedure is meant to be executed when OpenOCD enters run
-stage (@xref{Entering the Run Stage},) after @code{init_targets}. The idea to have spearate @code{init_targets} and
-@code{init_board} procedures is to allow the first one to configure everything target specific (internal flash,
-internal RAM, etc.) and the second one to configure everything board specific (reset signals, chip frequency,
-reset-init event handler, external memory, etc.). Additionally ``linear'' board config file will most likely fail when
-target config file uses @code{init_targets} scheme (``linear'' script is executed before @code{init} and
-@code{init_targets} - after), so separating these two configuration stages is very convenient, as the easiest way to
-overcome this problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
-need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
-
-Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
+The concept of @code{init_board} procedure is very similar to @code{init_targets}
+(@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
+configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
+(@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
+separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
+everything target specific (internal flash, internal RAM, etc.) and the second one to configure
+everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
+Additionally ``linear'' board config file will most likely fail when target config file uses
+@code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
+so separating these two configuration stages is very convenient, as the easiest way to overcome this
+problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
+need to override @code{init_targets} defined in target config files when they only need to add some specifics.
+
+Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
the original), allowing greater code reuse.
@example
@}
# TAP identifiers may change as chips mature, for example with
-# new revision fields (the "3" here). Pick a good default; you
+# new revision fields (the "3" here). Pick a good default; you
# can pass several such identifiers to the "jtag newtap" command.
if @{ [info exists CPUTAPID ] @} @{
set _CPUTAPID $CPUTAPID
@end example
There are more complex examples too, with chips that have
-multiple TAPs. Ones worth looking at include:
+multiple TAPs. Ones worth looking at include:
@itemize
@item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
-work-area-size 0x4000 -work-area-backup 0
@end example
-@anchor{Define CPU targets working in SMP}
+@anchor{definecputargetsworkinginsmp}
@subsection Define CPU targets working in SMP
@cindex SMP
After setting targets, you can define a list of targets working in SMP.
@example
set _TARGETNAME_1 $_CHIPNAME.cpu1
set _TARGETNAME_2 $_CHIPNAME.cpu2
-target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
-coreid 0 -dbgbase $_DAP_DBG1
-target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
-coreid 1 -dbgbase $_DAP_DBG2
#define 2 targets working in smp.
target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
@end example
-In the above example on cortex_a8, 2 cpus are working in SMP.
+In the above example on cortex_a, 2 cpus are working in SMP.
In SMP only one GDB instance is created and :
@itemize @bullet
@item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
@item resume command triggers the write context and the restart of all targets in the list.
@item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
@item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
-displayed by the GDB session @pxref{Using openocd SMP with GDB}.
+displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
@end itemize
-The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
+The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
command have been implemented.
@itemize @bullet
-@item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
-@item cortex_a8 smp_off : disable SMP mode, the current target is the one
+@item cortex_a smp_on : enable SMP mode, behaviour is as described above.
+@item cortex_a smp_off : disable SMP mode, the current target is the one
displayed in the GDB session, only this target is now controlled by GDB
session. This behaviour is useful during system boot up.
-@item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
+@item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
following example.
@end itemize
@example
->cortex_a8 smp_gdb
+>cortex_a smp_gdb
gdb coreid 0 -> -1
#0 : coreid 0 is displayed to GDB ,
#-> -1 : next resume triggers a real resume
-> cortex_a8 smp_gdb 1
+> cortex_a smp_gdb 1
gdb coreid 0 -> 1
#0 :coreid 0 is displayed to GDB ,
#->1 : next resume displays coreid 1 to GDB
> resume
-> cortex_a8 smp_gdb
+> cortex_a smp_gdb
gdb coreid 1 -> 1
#1 :coreid 1 is displayed to GDB ,
#->1 : next resume displays coreid 1 to GDB
-> cortex_a8 smp_gdb -1
+> cortex_a smp_gdb -1
gdb coreid 1 -> -1
#1 :coreid 1 is displayed to GDB,
#->-1 : next resume triggers a real resume
@subsection Chip Reset Setup
As a rule, you should put the @command{reset_config} command
-into the board file. Most things you think you know about a
+into the board file. Most things you think you know about a
chip can be tweaked by the board.
Some chips have specific ways the TRST and SRST signals are
Such a handler might write to chip registers to force a reset,
use a JRC to do that (preferable -- the target may be wedged!),
or force a watchdog timer to trigger.
-(For Cortex-M3 targets, this is not necessary. The target
+(For Cortex-M targets, this is not necessary. The target
driver knows how to use trigger an NVIC reset when SRST is
not available.)
That means that after reset (and potentially, as OpenOCD
first starts up) they must use a slower JTAG clock rate
than they will use later.
-@xref{JTAG Speed}.
+@xref{jtagspeed,,JTAG Speed}.
@quotation Important
When you are debugging code that runs right after chip
look at how you are setting up JTAG clocking.
@end quotation
-@anchor{The init_targets procedure}
+@anchor{theinittargetsprocedure}
@subsection The init_targets procedure
@cindex init_targets procedure
-Target config files can either be ``linear'' (script executed line-by-line when parsed in configuration stage,
-@xref{Configuration Stage},) or they can contain a special procedure called @code{init_targets}, which will be executed
-when entering run stage (after parsing all config files or after @code{init} command, @xref{Entering the Run Stage}.)
-Such procedure can be overriden by ``next level'' script (which sources the original). This concept faciliates code
-reuse when basic target config files provide generic configuration procedures and @code{init_targets} procedure, which
-can then be sourced and enchanced or changed in a ``more specific'' target config file. This is not possible with
-``linear'' config scripts, because sourcing them executes every initialization commands they provide.
+Target config files can either be ``linear'' (script executed line-by-line when parsed in
+configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
+procedure called @code{init_targets}, which will be executed when entering run stage
+(after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
+Such procedure can be overriden by ``next level'' script (which sources the original).
+This concept faciliates code reuse when basic target config files provide generic configuration
+procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
+a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
+because sourcing them executes every initialization commands they provide.
@example
### generic_file.cfg ###
@}
@end example
-The easiest way to convert ``linear'' config files to @code{init_targets} version is to enclose every line of ``code''
-(i.e. not @code{source} commands, procedures, etc.) in this procedure.
+The easiest way to convert ``linear'' config files to @code{init_targets} version is to
+enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
For an example of this scheme see LPC2000 target config files.
-The @code{init_boards} procedure is a similar concept concerning board config files (@xref{The init_board procedure}.)
+The @code{init_boards} procedure is a similar concept concerning board config files
+(@xref{theinitboardprocedure,,The init_board procedure}.)
+
+@anchor{theinittargeteventsprocedure}
+@subsection The init_target_events procedure
+@cindex init_target_events procedure
+
+A special procedure called @code{init_target_events} is run just after
+@code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
+procedure}.) and before @code{init_board}
+(@xref{theinitboardprocedure,,The init_board procedure}.) It is used
+to set up default target events for the targets that do not have those
+events already assigned.
@subsection ARM Core Specific Hacks
If present, the MMU, the MPU and the CACHE should be disabled.
Some ARM cores are equipped with trace support, which permits
-examination of the instruction and data bus activity. Trace
+examination of the instruction and data bus activity. Trace
activity is controlled through an ``Embedded Trace Module'' (ETM)
-on one of the core's scan chains. The ETM emits voluminous data
-through a ``trace port''. (@xref{ARM Hardware Tracing}.)
+on one of the core's scan chains. The ETM emits voluminous data
+through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
If you are using an external trace port,
configure it in your board config file.
If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
@item pxa270 - again - CS0 flash - it goes in the board file.
@end itemize
-@anchor{Translating Configuration Files}
+@anchor{translatingconfigurationfiles}
@section Translating Configuration Files
@cindex translation
If you have a configuration file for another hardware debugger
used to specify what TCP/IP ports are used, and how GDB should be
supported.
-@anchor{Configuration Stage}
+@anchor{configurationstage}
@section Configuration Stage
@cindex configuration stage
@cindex config command
After it leaves this stage, configuration commands may no
longer be issued.
-@anchor{Entering the Run Stage}
+@anchor{enteringtherunstage}
@section Entering the Run Stage
The first thing OpenOCD does after leaving the configuration
@deffn {Config Command} init
This command terminates the configuration stage and
-enters the run stage. This helps when you need to have
+enters the run stage. This helps when you need to have
the startup scripts manage tasks such as resetting the target,
programming flash, etc. To reset the CPU upon startup, add "init" and
"reset" at the end of the config script or at the end of the OpenOCD
openocd.cfg file to force OpenOCD to ``initialize'' and make the
targets ready. For example: If your openocd.cfg file needs to
read/write memory on your target, @command{init} must occur before
-the memory read/write commands. This includes @command{nand probe}.
+the memory read/write commands. This includes @command{nand probe}.
@end deffn
@deffn {Overridable Procedure} jtag_init
(or @command{jtag arp_init-reset}).
@end deffn
-@anchor{TCP/IP Ports}
+@anchor{tcpipports}
@section TCP/IP Ports
@cindex TCP port
@cindex server
When specified as zero, this port is not activated.
@end deffn
-@anchor{GDB Configuration}
+@anchor{gdbconfiguration}
@section GDB Configuration
@cindex GDB
@cindex GDB configuration
You can reconfigure some GDB behaviors if needed.
The ones listed here are static and global.
-@xref{Target Configuration}, about configuring individual targets.
-@xref{Target Events}, about configuring target-specific event handling.
+@xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
+@xref{targetevents,,Target Events}, about configuring target-specific event handling.
-@anchor{gdb_breakpoint_override}
+@anchor{gdbbreakpointoverride}
@deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
Force breakpoint type for gdb @command{break} commands.
This option supports GDB GUIs which don't
distinguish hard versus soft breakpoints, if the default OpenOCD and
-GDB behaviour is not sufficient. GDB normally uses hardware
+GDB behaviour is not sufficient. GDB normally uses hardware
breakpoints if the memory map has been set up for flash regions.
@end deffn
-@anchor{gdb_flash_program}
+@anchor{gdbflashprogram}
@deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
Set to @option{enable} to cause OpenOCD to program the flash memory when a
vFlash packet is received.
using the GDB load command. @command{gdb_flash_program enable} must also be enabled
for flash programming to work.
Default behaviour is @option{enable}.
-@xref{gdb_flash_program}.
+@xref{gdbflashprogram,,gdb_flash_program}.
@end deffn
@deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
use @option{enable} see these errors reported.
@end deffn
-@anchor{Event Polling}
+@deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
+Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
+The default behaviour is @option{disable}.
+@end deffn
+
+@deffn {Command} gdb_save_tdesc
+Saves the target descripton file to the local file system.
+
+The file name is @i{target_name}.xml.
+@end deffn
+
+@anchor{eventpolling}
@section Event Polling
Hardware debuggers are parts of asynchronous systems,
@deffn Command poll [@option{on}|@option{off}]
Poll the current target for its current state.
-(Also, @pxref{target curstate}.)
+(Also, @pxref{targetcurstate,,target curstate}.)
If that target is in debug mode, architecture
specific information about the current state is printed.
An optional parameter
@cindex interface config file
Correctly installing OpenOCD includes making your operating system give
-OpenOCD access to debug adapters. Once that has been done, Tcl commands
+OpenOCD access to debug adapters. Once that has been done, Tcl commands
are used to select which one is used, and to configure how it is used.
@quotation Note
Because OpenOCD started out with a focus purely on JTAG, you may find
places where it wrongly presumes JTAG is the only transport protocol
-in use. Be aware that recent versions of OpenOCD are removing that
-limitation. JTAG remains more functional than most other transports.
+in use. Be aware that recent versions of OpenOCD are removing that
+limitation. JTAG remains more functional than most other transports.
Other transports do not support boundary scan operations, or may be
-specific to a given chip vendor. Some might be usable only for
+specific to a given chip vendor. Some might be usable only for
programming flash memory, instead of also for debugging.
@end quotation
@c chooses among list of bit configs ... only one option
@end deffn
+@deffn {Interface Driver} {cmsis-dap}
+ARM CMSIS-DAP compliant based adapter.
+
+@deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
+The vendor ID and product ID of the CMSIS-DAP device. If not specified
+the driver will attempt to auto detect the CMSIS-DAP device.
+Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
+@example
+cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
+@end example
+@end deffn
+
+@deffn {Config Command} {cmsis_dap_serial} [serial]
+Specifies the @var{serial} of the CMSIS-DAP device to use.
+If not specified, serial numbers are not considered.
+@end deffn
+
+@deffn {Command} {cmsis-dap info}
+Display various device information, like hardware version, firmware version, current bus status.
+@end deffn
+@end deffn
+
@deffn {Interface Driver} {dummy}
A dummy software-only driver for debugging.
@end deffn
@deffn {Interface Driver} {ft2232}
FTDI FT2232 (USB) based devices over one of the userspace libraries.
+
+Note that this driver has several flaws and the @command{ftdi} driver is
+recommended as its replacement.
+
These interfaces have several commands, used to configure the driver
before initializing the JTAG scan chain:
@item @b{axm0432_jtag} Axiom AXM-0432
@item @b{comstick} Hitex STR9 comstick
@item @b{cortino} Hitex Cortino JTAG interface
-@item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
+@item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
either for the local Cortex-M3 (SRST only)
or in a passthrough mode (neither SRST nor TRST)
This layout can not support the SWO trace mechanism, and should be
used only for older boards (before rev C).
-@item @b{luminary_icdi} This layout should be used with most Luminary
+@item @b{luminary_icdi} This layout should be used with most TI/Luminary
eval boards, including Rev C LM3S811 eval boards and the eponymous
ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
-to debug some other target. It can support the SWO trace mechanism.
+to debug some other target. It can support the SWO trace mechanism.
@item @b{flyswatter} Tin Can Tools Flyswatter
@item @b{icebear} ICEbear JTAG adapter from Section 5
@item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
@end deffn
+@deffn {Config Command} {ft2232_channel} channel
+Used to select the channel of the ft2232 chip to use (between 1 and 4).
+The default value is 1.
+@end deffn
+
For example, the interface config file for a
Turtelizer JTAG Adapter looks something like this:
@end example
@end deffn
+@deffn {Interface Driver} {ftdi}
+This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
+Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
+It is a complete rewrite to address a large number of problems with the ft2232
+interface driver.
+
+The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
+bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
+consistently faster than the ft2232 driver, sometimes several times faster.
+
+A major improvement of this driver is that support for new FTDI based adapters
+can be added competely through configuration files, without the need to patch
+and rebuild OpenOCD.
+
+The driver uses a signal abstraction to enable Tcl configuration files to
+define outputs for one or several FTDI GPIO. These outputs can then be
+controlled using the @command{ftdi_set_signal} command. Special signal names
+are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
+will be used for their customary purpose.
+
+Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
+be controlled differently. In order to support tristateable signals such as
+nSRST, both a data GPIO and an output-enable GPIO can be specified for each
+signal. The following output buffer configurations are supported:
+
+@itemize @minus
+@item Push-pull with one FTDI output as (non-)inverted data line
+@item Open drain with one FTDI output as (non-)inverted output-enable
+@item Tristate with one FTDI output as (non-)inverted data line and another
+ FTDI output as (non-)inverted output-enable
+@item Unbuffered, using the FTDI GPIO as a tristate output directly by
+ switching data and direction as necessary
+@end itemize
+
+These interfaces have several commands, used to configure the driver
+before initializing the JTAG scan chain:
+
+@deffn {Config Command} {ftdi_vid_pid} [vid pid]+
+The vendor ID and product ID of the adapter. If not specified, the FTDI
+default values are used.
+Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
+@example
+ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
+@end example
+@end deffn
+
+@deffn {Config Command} {ftdi_device_desc} description
+Provides the USB device description (the @emph{iProduct string})
+of the adapter. If not specified, the device description is ignored
+during device selection.
+@end deffn
+
+@deffn {Config Command} {ftdi_serial} serial-number
+Specifies the @var{serial-number} of the adapter to use,
+in case the vendor provides unique IDs and more than one adapter
+is connected to the host.
+If not specified, serial numbers are not considered.
+(Note that USB serial numbers can be arbitrary Unicode strings,
+and are not restricted to containing only decimal digits.)
+@end deffn
+
+@deffn {Config Command} {ftdi_channel} channel
+Selects the channel of the FTDI device to use for MPSSE operations. Most
+adapters use the default, channel 0, but there are exceptions.
+@end deffn
+
+@deffn {Config Command} {ftdi_layout_init} data direction
+Specifies the initial values of the FTDI GPIO data and direction registers.
+Each value is a 16-bit number corresponding to the concatenation of the high
+and low FTDI GPIO registers. The values should be selected based on the
+schematics of the adapter, such that all signals are set to safe levels with
+minimal impact on the target system. Avoid floating inputs, conflicting outputs
+and initially asserted reset signals.
+@end deffn
+
+@deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
+Creates a signal with the specified @var{name}, controlled by one or more FTDI
+GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
+register bitmasks to tell the driver the connection and type of the output
+buffer driving the respective signal. @var{data_mask} is the bitmask for the
+pin(s) connected to the data input of the output buffer. @option{-ndata} is
+used with inverting data inputs and @option{-data} with non-inverting inputs.
+The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
+not-output-enable) input to the output buffer is connected.
+
+Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
+simple open-collector transistor driver would be specified with @option{-oe}
+only. In that case the signal can only be set to drive low or to Hi-Z and the
+driver will complain if the signal is set to drive high. Which means that if
+it's a reset signal, @command{reset_config} must be specified as
+@option{srst_open_drain}, not @option{srst_push_pull}.
+
+A special case is provided when @option{-data} and @option{-oe} is set to the
+same bitmask. Then the FTDI pin is considered being connected straight to the
+target without any buffer. The FTDI pin is then switched between output and
+input as necessary to provide the full set of low, high and Hi-Z
+characteristics. In all other cases, the pins specified in a signal definition
+are always driven by the FTDI.
+
+If @option{-alias} or @option{-nalias} is used, the signal is created
+identical (or with data inverted) to an already specified signal
+@var{name}.
+@end deffn
+
+@deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
+Set a previously defined signal to the specified level.
+@itemize @minus
+@item @option{0}, drive low
+@item @option{1}, drive high
+@item @option{z}, set to high-impedance
+@end itemize
+@end deffn
+
+For example adapter definitions, see the configuration files shipped in the
+@file{interface/ftdi} directory.
+@end deffn
+
@deffn {Interface Driver} {remote_bitbang}
Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
with a remote process and sends ASCII encoded bitbang requests to that process
@deffn {Interface Driver} {usb_blaster}
USB JTAG/USB-Blaster compatibles over one of the userspace libraries
-for FTDI chips. These interfaces have several commands, used to
+for FTDI chips. These interfaces have several commands, used to
configure the driver before initializing the JTAG scan chain:
@deffn {Config Command} {usb_blaster_device_desc} description
@end example
@end deffn
-@deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
-Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
-female JTAG header). These pins can be used as SRST and/or TRST provided the
-appropriate connections are made on the target board.
+@deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
+Sets the state or function of the unused GPIO pins on USB-Blasters
+(pins 6 and 8 on the female JTAG header). These pins can be used as
+SRST and/or TRST provided the appropriate connections are made on the
+target board.
-For example, to use pin 6 as SRST (as with an AVR board):
+For example, to use pin 6 as SRST:
@example
-$_TARGETNAME configure -event reset-assert \
- "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
+usb_blaster_pin pin6 s
+reset_config srst_only
@end example
@end deffn
@end deffn
@deffn {Interface Driver} {jlink}
-Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
+Segger J-Link family of USB adapters. It currently supports JTAG and SWD transports.
@quotation Compatibility Note
Segger released many firmware versions for the many harware versions they
@deffn {Config} {jlink pid} val
Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
@end deffn
+@deffn {Config} {jlink serial} serial-number
+Set the @var{serial-number} of the interface, in case more than one adapter is connected to the host.
+If not specified, serial numbers are not considered.
+
+Note that there may be leading zeros in the @var{serial-number} string
+that will not show in the Segger software, but must be specified here.
+Debug level 3 output contains serial numbers if there is a mismatch.
+
+As a configuration command, it can be used only before 'init'.
+@end deffn
@end deffn
@deffn {Interface Driver} {parport}
You can do something similar with many digital multimeters, but note
that you'll probably need to run the clock continuously for several
-seconds before it decides what clock rate to show. Adjust the
+seconds before it decides what clock rate to show. Adjust the
toggling time up or down until the measured clock rate is a good
match for the adapter_khz rate you specified; be conservative.
@end quotation
@end quotation
@end deffn
-@deffn {Interface Driver} {stlink}
-ST Micro ST-LINK adapter.
+@anchor{hla_interface}
+@deffn {Interface Driver} {hla}
+This is a driver that supports multiple High Level Adapters.
+This type of adapter does not expose some of the lower level api's
+that OpenOCD would normally use to access the target.
+
+Currently supported adapters include the ST STLINK and TI ICDI.
+STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
+versions of firmware where serial number is reset after first use. Suggest
+using ST firmware update utility to upgrade STLINK firmware even if current
+version reported is V2.J21.S4.
-@deffn {Config Command} {stlink_device_desc} description
+@deffn {Config Command} {hla_device_desc} description
Currently Not Supported.
@end deffn
-@deffn {Config Command} {stlink_serial} serial
-Currently Not Supported.
+@deffn {Config Command} {hla_serial} serial
+Specifies the serial number of the adapter.
@end deffn
-@deffn {Config Command} {stlink_layout} (@option{sg}|@option{usb})
-Specifies the stlink layout to use.
+@deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
+Specifies the adapter layout to use.
@end deffn
-@deffn {Config Command} {stlink_vid_pid} vid pid
-The vendor ID and product ID of the STLINK device.
+@deffn {Config Command} {hla_vid_pid} vid pid
+The vendor ID and product ID of the device.
@end deffn
-@deffn {Config Command} {stlink_api} api_level
-Manually sets the stlink api used, valid options are 1 or 2.
+@deffn {Command} {hla_command} command
+Execute a custom adapter-specific command. The @var{command} string is
+passed as is to the underlying adapter layout handler.
@end deffn
@end deffn
No arguments: print status.
@end deffn
+@deffn {Interface Driver} {bcm2835gpio}
+This SoC is present in Raspberry Pi which is a cheap single-board computer
+exposing some GPIOs on its expansion header.
+
+The driver accesses memory-mapped GPIO peripheral registers directly
+for maximum performance, but the only possible race condition is for
+the pins' modes/muxing (which is highly unlikely), so it should be
+able to coexist nicely with both sysfs bitbanging and various
+peripherals' kernel drivers. The driver restores the previous
+configuration on exit.
+
+See @file{interface/raspberrypi-native.cfg} for a sample config and
+pinout.
+
+@end deffn
+
@section Transport Configuration
@cindex Transport
As noted earlier, depending on the version of OpenOCD you use,
version of OpenOCD.
@end deffn
-@deffn Command {transport select} transport_name
+@deffn Command {transport select} @option{transport_name}
Select which of the supported transports to use in this OpenOCD session.
-The transport must be supported by the debug adapter hardware and by the
-version of OPenOCD you are using (including the adapter's driver).
-No arguments: returns name of session's selected transport.
+
+When invoked with @option{transport_name}, attempts to select the named
+transport. The transport must be supported by the debug adapter
+hardware and by the version of OpenOCD you are using (including the
+adapter's driver).
+
+If no transport has been selected and no @option{transport_name} is
+provided, @command{transport select} auto-selects the first transport
+supported by the debug adapter.
+
+@command{transport select} always returns the name of the session's selected
+transport, if any.
@end deffn
@subsection JTAG Transport
each of which must be explicitly declared.
JTAG supports both debugging and boundary scan testing.
Flash programming support is built on top of debug support.
+
+JTAG transport is selected with the command @command{transport select
+jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
+driver}, in which case the command is @command{transport select
+hla_jtag}.
+
@subsection SWD Transport
@cindex SWD
@cindex Serial Wire Debug
SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
Debug Access Point (DAP, which must be explicitly declared.
(SWD uses fewer signal wires than JTAG.)
-SWD is debug-oriented, and does not support boundary scan testing.
+SWD is debug-oriented, and does not support boundary scan testing.
Flash programming support is built on top of debug support.
(Some processors support both JTAG and SWD.)
+
+SWD transport is selected with the command @command{transport select
+swd}. Unless your adapter uses @ref{hla_interface,the hla interface
+driver}, in which case the command is @command{transport select
+hla_swd}.
+
@deffn Command {swd newdap} ...
Declares a single DAP which uses SWD transport.
Parameters are currently the same as "jtag newtap" but this is
@cindex SPI
@cindex Serial Peripheral Interface
The Serial Peripheral Interface (SPI) is a general purpose transport
-which uses four wire signaling. Some processors use it as part of a
+which uses four wire signaling. Some processors use it as part of a
solution for flash programming.
-@anchor{JTAG Speed}
+@anchor{jtagspeed}
@section JTAG Speed
JTAG clock setup is part of system setup.
It @emph{does not belong with interface setup} since any interface
@code{reset-init} target event handler after it reprograms those
CPU clocks, or manually (if something else, such as a boot loader,
sets up those clocks).
-@xref{Target Events}.
+@xref{targetevents,,Target Events}.
When the initial low JTAG speed is a chip characteristic, perhaps
because of a required oscillator speed, provide such a handler
in the target config file.
@deffn {Command} adapter_khz max_speed_kHz
A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
JTAG interfaces usually support a limited number of
-speeds. The speed actually used won't be faster
+speeds. The speed actually used won't be faster
than the speed specified.
Chip data sheets generally include a top JTAG clock rate.
For example, most ARM cores accept at most one sixth of the CPU clock.
Speed 0 (khz) selects RTCK method.
-@xref{FAQ RTCK}.
+@xref{faqrtck,,FAQ RTCK}.
If your system uses RTCK, you won't need to change the
JTAG clocking after setup.
Not all interfaces, boards, or targets support ``rtck''.
configuration. This can also be quite confusing.
Resets also interact with @var{reset-init} event handlers,
which do things like setting up clocks and DRAM, and
-JTAG clock rates. (@xref{JTAG Speed}.)
+JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
They can also interact with JTAG routers.
Please see the various board files for examples.
@item
@emph{System Reset} ... the @emph{SRST} hardware signal
resets all chips connected to the JTAG adapter, such as processors,
-power management chips, and I/O controllers. Normally resets triggered
+power management chips, and I/O controllers. Normally resets triggered
with this signal behave exactly like pressing a RESET button.
@item
@emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
device's TAP controller just puts that controller into a known state.
@item
@emph{Emulation Reset} ... many devices can be reset through JTAG
-commands. These resets are often distinguishable from system
+commands. These resets are often distinguishable from system
resets, either explicitly (a "reset reason" register says so)
or implicitly (not all parts of the chip get reset).
@item
This is the behavior required to support the @command{reset halt}
and @command{reset init} commands; after @command{reset init} a
board-specific script might do things like setting up DRAM.
-(@xref{Reset Command}.)
+(@xref{resetcommand,,Reset Command}.)
-@anchor{SRST and TRST Issues}
+@anchor{srstandtrstissues}
@section SRST and TRST Issues
Because SRST and TRST are hardware signals, they can have a
-variety of system-specific constraints. Some of the most
+variety of system-specific constraints. Some of the most
common issues are:
@itemize @bullet
@item @emph{Signal not available} ... Some boards don't wire
-SRST or TRST to the JTAG connector. Some JTAG adapters don't
+SRST or TRST to the JTAG connector. Some JTAG adapters don't
support such signals even if they are wired up.
Use the @command{reset_config} @var{signals} options to say
when either of those signals is not connected.
@item @emph{Timing} ... Reset circuitry like a resistor/capacitor
delay circuit, reset supervisor, or on-chip features can extend
the effect of a JTAG adapter's reset for some time after the adapter
-stops issuing the reset. For example, there may be chip or board
+stops issuing the reset. For example, there may be chip or board
requirements that all reset pulses last for at least a
certain amount of time; and reset buttons commonly have
hardware debouncing.
@item @emph{Drive type} ... Reset lines often have a pullup
resistor, letting the JTAG interface treat them as open-drain
-signals. But that's not a requirement, so the adapter may need
+signals. But that's not a requirement, so the adapter may need
to use push/pull output drivers.
Also, with weak pullups it may be advisable to drive
signals to both levels (push/pull) to minimize rise times.
Use the @command{reset_config} @var{trst_type} and
@var{srst_type} parameters to say how to drive reset signals.
-@item @emph{Special initialization} ... Targets sometimes need
+@item @emph{Special initialization} ... Targets sometimes need
special JTAG initialization sequences to handle chip-specific
issues (not limited to errata).
For example, certain JTAG commands might need to be issued while
configuration scripts.
Information earlier in this section describes the kind of problems
-the command is intended to address (@pxref{SRST and TRST Issues}).
+the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
As a rule this command belongs only in board config files,
describing issues like @emph{board doesn't connect TRST};
or in user config files, addressing limitations derived
with a board that only wires up SRST.)
The @var{mode_flag} options can be specified in any order, but only one
-of each type -- @var{signals}, @var{combination},
-@var{gates},
-@var{trst_type},
-and @var{srst_type} -- may be specified at a time.
+of each type -- @var{signals}, @var{combination}, @var{gates},
+@var{trst_type}, @var{srst_type} and @var{connect_type}
+-- may be specified at a time.
If you don't provide a new value for a given type, its previous
value (perhaps the default) is unchanged.
For example, this means that you don't need to say anything at all about
while SRST is asserted.
Its converse is @option{srst_nogate}, indicating that JTAG commands
can safely be issued while SRST is active.
+
+@item
+The @var{connect_type} tokens control flags that describe some cases where
+SRST is asserted while connecting to the target. @option{srst_nogate}
+is required to use this option.
+@option{connect_deassert_srst} (default)
+indicates that SRST will not be asserted while connecting to the target.
+Its converse is @option{connect_assert_srst}, indicating that SRST will
+be asserted before any target connection.
+Only some targets support this feature, STM32 and STR9 are examples.
+This feature is useful if you are unable to connect to your target due
+to incorrect options byte config or illegal program execution.
@end itemize
The optional @var{trst_type} and @var{srst_type} parameters allow the
-driver mode of each reset line to be specified. These values only affect
+driver mode of each reset line to be specified. These values only affect
JTAG interfaces with support for different driver modes, like the Amontec
-JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
+JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
relevant signal (TRST or SRST) is not connected.
@itemize
@xref{JTAG Commands}.
When you find a working sequence, it can be used to override
@command{jtag_init}, which fires during OpenOCD startup
-(@pxref{Configuration Stage});
+(@pxref{configurationstage,,Configuration Stage});
or @command{init_reset}, which fires during reset processing.
You might also want to provide some project-specific reset
-schemes. For example, on a multi-target board the standard
+schemes. For example, on a multi-target board the standard
@command{reset} command would reset all targets, but you
may need the ability to reset only one target at time and
thus want to avoid using the board-wide SRST signal.
TAPs serve many roles, including:
@itemize @bullet
-@item @b{Debug Target} A CPU TAP can be used as a GDB debug target
-@item @b{Flash Programing} Some chips program the flash directly via JTAG.
+@item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
+@item @b{Flash Programming} Some chips program the flash directly via JTAG.
Others do it indirectly, making a CPU do it.
@item @b{Program Download} Using the same CPU support GDB uses,
you can initialize a DRAM controller, download code to DRAM, and then
start running that code.
@item @b{Boundary Scan} Most chips support boundary scan, which
helps test for board assembly problems like solder bridges
-and missing connections
+and missing connections.
@end itemize
OpenOCD must know about the active TAPs on your board(s).
@cindex scan chain
TAPs are part of a hardware @dfn{scan chain},
-which is daisy chain of TAPs.
+which is a daisy chain of TAPs.
They also need to be added to
OpenOCD's software mirror of that hardware list,
giving each member a name and associating other data with it.
@end verbatim
OpenOCD can detect some of that information, but not all
-of it. @xref{Autoprobing}.
-Unfortunately those TAPs can't always be autoconfigured,
+of it. @xref{autoprobing,,Autoprobing}.
+Unfortunately, those TAPs can't always be autoconfigured,
because not all devices provide good support for that.
JTAG doesn't require supporting IDCODE instructions, and
chips with JTAG routers may not link TAPs into the chain
Board configuration files combine all the targets on a board,
and so forth.
Note that @emph{the order in which TAPs are declared is very important.}
-It must match the order in the JTAG scan chain, both inside
-a single chip and between them.
-@xref{FAQ TAP Order}.
+That declaration order must match the order in the JTAG scan chain,
+both inside a single chip and between them.
+@xref{faqtaporder,,FAQ TAP Order}.
For example, the ST Microsystems STR912 chip has
three separate TAPs@footnote{See the ST
jtag newtap str912 bs ... params ...
@end example
-Actual config files use a variable instead of literals like
-@option{str912}, to support more than one chip of each type.
-@xref{Config File Guidelines}.
+Actual config files typically use a variable such as @code{$_CHIPNAME}
+instead of literals like @option{str912}, to support more than one chip
+of each type. @xref{Config File Guidelines}.
@deffn Command {jtag names}
Returns the names of all current TAPs in the scan chain.
enable or disable TAPs dynamically.
@end deffn
-@c FIXME! "jtag cget" should be able to return all TAP
+@c FIXME! "jtag cget" should be able to return all TAP
@c attributes, like "$target_name cget" does for targets.
@c Probably want "jtag eventlist", and a "tap-reset" event
For example: @code{xilinx.tap}, @code{str912.flash},
@code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
Many other commands use that dotted.name to manipulate or
-refer to the TAP. For example, CPU configuration uses the
+refer to the TAP. For example, CPU configuration uses the
name, as does declaration of NAND or NOR flash banks.
The components of a dotted name should follow ``C'' symbol
-name rules: start with an alphabetic character, then numbers
+name rules: start with an alphabetic character, then numbers
and underscores are OK; while others (including dots!) are not.
-@quotation Tip
-In older code, JTAG TAPs were numbered from 0..N.
-This feature is still present.
-However its use is highly discouraged, and
-should not be relied on; it will be removed by mid-2010.
-Update all of your scripts to use TAP names rather than numbers,
-by paying attention to the runtime warnings they trigger.
-Using TAP numbers in target configuration scripts prevents
-reusing those scripts on boards with multiple targets.
-@end quotation
-
@section TAP Declaration Commands
@c shouldn't this be(come) a {Config Command}?
-@anchor{jtag newtap}
@deffn Command {jtag newtap} chipname tapname configparams...
Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
and configured according to the various @var{configparams}.
and should follow this convention:
@itemize @bullet
-@item @code{bs} -- For boundary scan if this is a seperate TAP;
+@item @code{bs} -- For boundary scan if this is a separate TAP;
@item @code{cpu} -- The main CPU of the chip, alternatively
@code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
-@code{arm1} and @code{arm2} on chips two ARMs, and so forth;
+@code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
@item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
@item @code{flash} -- If the chip has a flash TAP, like the str912;
-@item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
+@item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
-@item @code{tap} -- Should be used only FPGA or CPLD like devices
+@item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
with a single TAP;
@item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
@item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
-For example, the Freescale IMX31 has a SDMA (Smart DMA) with
+For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
a JTAG TAP; that TAP should be named @code{sdma}.
@end itemize
@itemize @bullet
@item @code{-disable} (or @code{-enable})
@*Use the @code{-disable} parameter to flag a TAP which is not
-linked in to the scan chain after a reset using either TRST
+linked into the scan chain after a reset using either TRST
or the JTAG state machine's @sc{reset} state.
You may use @code{-enable} to highlight the default state
(the TAP is linked in).
-@xref{Enabling and Disabling TAPs}.
-@item @code{-expected-id} @var{number}
+@xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
+@item @code{-expected-id} @var{NUMBER}
@*A non-zero @var{number} represents a 32-bit IDCODE
which you expect to find when the scan chain is examined.
These codes are not required by all JTAG devices.
values that were found but not included in the list.
Provide this value if at all possible, since it lets OpenOCD
-tell when the scan chain it sees isn't right. These values
+tell when the scan chain it sees isn't right. These values
are provided in vendors' chip documentation, usually a technical
-reference manual. Sometimes you may need to probe the JTAG
+reference manual. Sometimes you may need to probe the JTAG
hardware to find these values.
-@xref{Autoprobing}.
+@xref{autoprobing,,Autoprobing}.
@item @code{-ignore-version}
@*Specify this to ignore the JTAG version field in the @code{-expected-id}
-option. When vendors put out multiple versions of a chip, or use the same
+option. When vendors put out multiple versions of a chip, or use the same
JTAG-level ID for several largely-compatible chips, it may be more practical
to ignore the version field than to update config files to handle all of
the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
on entry to the @sc{ircapture} state, such as 0x01.
JTAG requires the two LSBs of this value to be 01.
By default, @code{-ircapture} and @code{-irmask} are set
-up to verify that two-bit value. You may provide
-additional bits, if you know them, or indicate that
+up to verify that two-bit value. You may provide
+additional bits if you know them, or indicate that
a TAP doesn't conform to the JTAG specification.
@item @code{-irmask} @var{NUMBER}
@*A mask used with @code{-ircapture}
@section Other TAP commands
-@deffn Command {jtag cget} dotted.name @option{-event} name
-@deffnx Command {jtag configure} dotted.name @option{-event} name string
+@deffn Command {jtag cget} dotted.name @option{-event} event_name
+@deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
At this writing this TAP attribute
mechanism is used only for event handling.
(It is not a direct analogue of the @code{cget}/@code{configure}
The @code{cget} subcommand returns that handler.
@end deffn
-@anchor{TAP Events}
@section TAP Events
@cindex events
@cindex TAP events
@* The scan chain has been reset and verified.
This handler may enable TAPs as needed.
@item @b{tap-disable}
-@* The TAP needs to be disabled. This handler should
+@* The TAP needs to be disabled. This handler should
implement @command{jtag tapdisable}
by issuing the relevant JTAG commands.
@item @b{tap-enable}
-@* The TAP needs to be enabled. This handler should
+@* The TAP needs to be enabled. This handler should
implement @command{jtag tapenable}
by issuing the relevant JTAG commands.
@end itemize
-If you need some action after each JTAG reset, which isn't actually
+If you need some action after each JTAG reset which isn't actually
specific to any TAP (since you can't yet trust the scan chain's
contents to be accurate), you might:
@end example
-@anchor{Enabling and Disabling TAPs}
+@anchor{enablinganddisablingtaps}
@section Enabling and Disabling TAPs
@cindex JTAG Route Controller
@cindex jrc
In some systems, a @dfn{JTAG Route Controller} (JRC)
is used to enable and/or disable specific JTAG TAPs.
-Many ARM based chips from Texas Instruments include
-an ``ICEpick'' module, which is a JRC.
+Many ARM-based chips from Texas Instruments include
+an ``ICEPick'' module, which is a JRC.
Such chips include DaVinci and OMAP3 processors.
A given TAP may not be visible until the JRC has been
@end quotation
@end deffn
-@anchor{Autoprobing}
+@anchor{autoprobing}
@section Autoprobing
@cindex autoprobe
@cindex JTAG autoprobe
TAP configuration is the first thing that needs to be done
-after interface and reset configuration. Sometimes it's
+after interface and reset configuration. Sometimes it's
hard finding out what TAPs exist, or how they are identified.
Vendor documentation is not always easy to find and use.
@end example
When you start the server without any TAPs configured, it will
-attempt to autoconfigure the TAPs. There are two parts to this:
+attempt to autoconfigure the TAPs. There are two parts to this:
@enumerate
@item @emph{TAP discovery} ...
@end enumerate
In many cases your board will have a simple scan chain with just
-a single device. Here's what OpenOCD reported with one board
+a single device. Here's what OpenOCD reported with one board
that's a bit more complex:
@example
clock speed 8 kHz
-There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
+There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
@end example
Given that information, you should be able to either find some existing
-config files to use, or create your own. If you create your own, you
-would configure from the bottom up: first a @file{target.cfg} file
+config files to use, or create your own. If you create your own, you
+would configure from the bottom up: first a @file{target.cfg} file
with these TAPs, any targets associated with them, and any on-chip
resources; then a @file{board.cfg} with off-chip resources, clocking,
and so forth.
This chapter discusses how to set up GDB debug targets for CPUs.
You can also access these targets without GDB
(@pxref{Architecture and Core Commands},
-and @ref{Target State handling}) and
+and @ref{targetstatehandling,,Target State handling}) and
through various kinds of NAND and NOR flash commands.
If you have multiple CPUs you can have multiple such targets.
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* at91rm9200.cpu arm920t little at91rm9200.cpu running
- 1 MyTarget cortex_m3 little mychip.foo tap-disabled
+ 1 MyTarget cortex_m little mychip.foo tap-disabled
@end verbatim
One member of that list is the @dfn{current target}, which
Several commands let you examine the list of targets:
-@deffn Command {target count}
-@emph{Note: target numbers are deprecated; don't use them.
-They will be removed shortly after August 2010, including this command.
-Iterate target using @command{target names}, not by counting.}
-
-Returns the number of targets, @math{N}.
-The highest numbered target is @math{N - 1}.
-@example
-set c [target count]
-for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
- # Assuming you have created this function
- print_target_details $x
-@}
-@end example
-@end deffn
-
@deffn Command {target current}
Returns the name of the current target.
@end deffn
@end example
@end deffn
-@deffn Command {target number} number
-@emph{Note: target numbers are deprecated; don't use them.
-They will be removed shortly after August 2010, including this command.}
-
-The list of targets is numbered starting at zero.
-This command returns the name of the target at index @var{number}.
-@example
-set thename [target number $x]
-puts [format "Target %d is: %s\n" $x $thename]
-@end example
-@end deffn
-
@c yep, "target list" would have been better.
@c plus maybe "target setdefault".
@deffn Command targets [name]
-@emph{Note: the name of this command is plural. Other target
+@emph{Note: the name of this command is plural. Other target
command names are singular.}
With no parameter, this command displays a table of all known
only relevant on boards which have more than one target.
@end deffn
-@section Target CPU Types and Variants
+@section Target CPU Types
@cindex target type
@cindex CPU type
-@cindex CPU variant
Each target has a @dfn{CPU type}, as shown in the output of
-the @command{targets} command. You need to specify that type
+the @command{targets} command. You need to specify that type
when calling @command{target create}.
The CPU type indicates more than just the instruction set.
It also indicates how that instruction set is implemented,
(@pxref{Architecture and Core Commands}),
and more.
-For some CPU types, OpenOCD also defines @dfn{variants} which
-indicate differences that affect their handling.
-For example, a particular implementation bug might need to be
-worked around in some chip versions.
-
It's easy to see what target types are supported,
since there's a command to list them.
-However, there is currently no way to list what target variants
-are supported (other than by reading the OpenOCD source code).
-@anchor{target types}
+@anchor{targettypes}
@deffn Command {target types}
Lists all supported target types.
-At this writing, the supported CPU types and variants are:
+At this writing, the supported CPU types are:
@itemize @bullet
@item @code{arm11} -- this is a generation of ARMv6 cores
@item @code{arm9tdmi} -- this is an ARMv4 core
@item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
(Support for this is preliminary and incomplete.)
-@item @code{cortex_a8} -- this is an ARMv7 core with an MMU
-@item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
+@item @code{cortex_a} -- this is an ARMv7 core with an MMU
+@item @code{cortex_m} -- this is an ARMv7 core, supporting only the
compact Thumb2 instruction set.
@item @code{dragonite} -- resembles arm966e
@item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
(Support for this is still incomplete.)
@item @code{fa526} -- resembles arm920 (w/o Thumb)
@item @code{feroceon} -- resembles arm926
-@item @code{mips_m4k} -- a MIPS core. This supports one variant:
+@item @code{mips_m4k} -- a MIPS core
@item @code{xscale} -- this is actually an architecture,
-not a CPU type. It is based on the ARMv5 architecture.
-There are several variants defined:
+not a CPU type. It is based on the ARMv5 architecture.
+@item @code{openrisc} -- this is an OpenRISC 1000 core.
+The current implementation supports three JTAG TAP cores:
@itemize @minus
-@item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
-@code{pxa27x} ... instruction register length is 7 bits
-@item @code{pxa250}, @code{pxa255},
-@code{pxa26x} ... instruction register length is 5 bits
-@item @code{pxa3xx} ... instruction register length is 11 bits
+@item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
+@item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
+@item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
+@end itemize
+And two debug interfaces cores:
+@itemize @minus
+@item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
+@item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
@end itemize
@end itemize
@end deffn
while names like ARMv4, ARMv5, ARMv6, and ARMv7
reflect an architecture version implemented by a CPU design.
-@anchor{Target Configuration}
+@anchor{targetconfiguration}
@section Target Configuration
Before creating a ``target'', you must have added its TAP to the scan chain.
right after it adds all of the chip's TAPs to the scan chain.
Although you can set up a target in one step, it's often clearer if you
-use shorter commands and do it in two steps: create it, then configure
+use shorter commands and do it in two steps: create it, then configure
optional parts.
All operations on the target after it's created will use a new
command, created as part of target creation.
The two main things to configure after target creation are
a work area, which usually has target-specific defaults even
if the board setup code overrides them later;
-and event handlers (@pxref{Target Events}), which tend
+and event handlers (@pxref{targetevents,,Target Events}), which tend
to be much more board-specific.
The key steps you use might look something like this
@example
-target create MyTarget cortex_m3 -chain-position mychip.cpu
+target create MyTarget cortex_m -chain-position mychip.cpu
$MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
$MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
$MyTarget configure -event reset-init @{ myboard_reinit @}
purposes including additional configuration.
@itemize @bullet
-@item @var{target_name} ... is the name of the debug target.
+@item @var{target_name} ... is the name of the debug target.
By convention this should be the same as the @emph{dotted.name}
of the TAP associated with this target, which must be specified here
using the @code{-chain-position @var{dotted.name}} configparam.
This name is also used to create the target object command,
referred to here as @command{$target_name},
and in other places the target needs to be identified.
-@item @var{type} ... specifies the target type. @xref{target types}.
-@item @var{configparams} ... all parameters accepted by
+@item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
+@item @var{configparams} ... all parameters accepted by
@command{$target_name configure} are permitted.
If the target is big-endian, set it here with @code{-endian big}.
-If the variant matters, set it here with @code{-variant}.
You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
@end itemize
@emph{Warning:} changing some of these after setup is dangerous.
For example, moving a target from one TAP to another;
-and changing its endianness or variant.
+and changing its endianness.
@itemize @bullet
whether the CPU uses big or little endian conventions
@item @code{-event} @var{event_name} @var{event_body} --
-@xref{Target Events}.
+@xref{targetevents,,Target Events}.
Note that this updates a list of named event handlers.
Calling this twice with two different event names assigns
two different handlers, but calling it twice with the
same event name assigns only one handler.
-@item @code{-variant} @var{name} -- specifies a variant of the target,
-which OpenOCD needs to know about.
-
@item @code{-work-area-backup} (@option{0}|@option{1}) -- says
whether the work area gets backed up; by default,
@emph{it is not backed up.}
be used by most build systems, but the end is often unused.
@item @code{-work-area-size} @var{size} -- specify work are size,
-in bytes. The same size applies regardless of whether its physical
+in bytes. The same size applies regardless of whether its physical
or virtual address is being used.
@item @code{-work-area-phys} @var{address} -- set the work area
The value should normally correspond to a static mapping for the
@code{-work-area-phys} address, set up by the current operating system.
+@anchor{rtostype}
@item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
@var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
-@option{FreeRTOS}|@option{linux}.
+@option{FreeRTOS}|@option{linux}|@option{ChibiOS}|@option{embKernel}|@option{mqx}
+@xref{gdbrtossupport,,RTOS Support}.
@end itemize
@end deffn
@end example
@end deffn
-@anchor{target curstate}
+@anchor{targetcurstate}
@deffn Command {$target_name curstate}
Displays the current target state:
@code{debug-running},
@code{halted},
@code{reset},
@code{running}, or @code{unknown}.
-(Also, @pxref{Event Polling}.)
+(Also, @pxref{eventpolling,,Event Polling}.)
@end deffn
@deffn Command {$target_name eventlist}
Displays a table listing all event handlers
currently associated with this target.
-@xref{Target Events}.
+@xref{targetevents,,Target Events}.
@end deffn
@deffn Command {$target_name invoke-event} event_name
at the specified address @var{addr}.
@end deffn
-@anchor{Target Events}
+@anchor{targetevents}
@section Target Events
@cindex target events
@cindex events
@command{target create ... -event}.
The programmer's model matches the @code{-command} option used in Tcl/Tk
-buttons and events. The two examples below act the same, but one creates
+buttons and events. The two examples below act the same, but one creates
and invokes a small procedure while the other inlines it.
@example
mychip.cpu configure -event gdb-attach my_attach_proc
mychip.cpu configure -event gdb-attach @{
echo "Reset..."
- # To make flash probe and gdb load to flash work we need a reset init.
+ # To make flash probe and gdb load to flash work
+ # we need a reset init.
reset init
@}
@end example
@item @b{gdb-end}
@* When the target has halted and GDB is not doing anything (see early halt)
@item @b{gdb-flash-erase-start}
-@* Before the GDB flash process tries to erase the flash
+@* Before the GDB flash process tries to erase the flash (default is
+@code{reset init})
@item @b{gdb-flash-erase-end}
@* After the GDB flash process has finished erasing the flash
@item @b{gdb-flash-write-start}
@* Before GDB writes to the flash
@item @b{gdb-flash-write-end}
-@* After GDB writes to the flash
+@* After GDB writes to the flash (default is @code{reset halt})
@item @b{gdb-start}
@* Before the target steps, gdb is trying to start/resume the target
@item @b{halted}
@* After all targets have resumed
@item @b{resumed}
@* Target has resumed
+@item @b{trace-config}
+@* After target hardware trace configuration was changed
@end itemize
@node Flash Commands
This partially reflects different hardware technologies:
NOR flash usually supports direct CPU instruction and data bus access,
while data from a NAND flash must be copied to memory before it can be
-used. (SPI flash must also be copied to memory before use.)
+used. (SPI flash must also be copied to memory before use.)
However, the documentation also uses ``flash'' as a generic term;
for example, ``Put flash configuration in board-specific files''.
passing parameters as needed by the driver.
@item Operate on the flash via @command{flash subcommand}
@* Often commands to manipulate the flash are typed by a human, or run
-via a script in some automated way. Common tasks include writing a
+via a script in some automated way. Common tasks include writing a
boot loader, operating system, or other data.
@item GDB Flashing
@* Flashing via GDB requires the flash be configured via ``flash
bank'', and the GDB flash features be enabled.
-@xref{GDB Configuration}.
+@xref{gdbconfiguration,,GDB Configuration}.
@end enumerate
Many CPUs have the ablity to ``boot'' from the first flash bank.
JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
board by (re)installing working boot firmware.
-@anchor{NOR Configuration}
+@anchor{norconfiguration}
@section Flash Configuration Commands
@cindex flash configuration
@itemize @bullet
@item @var{name} ... may be used to reference the flash bank
-in other flash commands. A number is also available.
+in other flash commands. A number is also available.
@item @var{driver} ... identifies the controller driver
associated with the flash bank being declared.
This is usually @code{cfi} for external flash, or else
the name of a microcontroller with embedded flash memory.
-@xref{Flash Driver List}.
+@xref{flashdriverlist,,Flash Driver List}.
@item @var{base} ... Base address of the flash chip.
@item @var{size} ... Size of the chip, in bytes.
For some drivers, this value is detected from the hardware.
commands to the flash controller.
@comment Actually, it's currently a controller-specific parameter...
@item @var{driver_options} ... drivers may support, or require,
-additional parameters. See the driver-specific documentation
+additional parameters. See the driver-specific documentation
for more information.
@end itemize
@quotation Note
@end deffn
@comment the REAL name for this command is "ocd_flash_banks"
-@comment less confusing would be: "flash list" (like "nand list")
+@comment less confusing would be: "flash list" (like "nand list")
@deffn Command {flash banks}
Prints a one-line summary of each device that was
declared using @command{flash bank}, numbered from zero.
@cindex flash reading
@cindex flash writing
@cindex flash programming
+@anchor{flashprogrammingcommands}
One feature distinguishing NOR flash from NAND or serial flash technologies
is that for read access, it acts exactly like any other addressible memory.
This means you can use normal memory read commands like @command{mdw} or
@command{dump_image} with it, with no special @command{flash} subcommands.
-@xref{Memory access}, and @ref{Image access}.
+@xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
-Write access works differently. Flash memory normally needs to be erased
-before it's written. Erasing a sector turns all of its bits to ones, and
-writing can turn ones into zeroes. This is why there are special commands
+Write access works differently. Flash memory normally needs to be erased
+before it's written. Erasing a sector turns all of its bits to ones, and
+writing can turn ones into zeroes. This is why there are special commands
for interactive erasing and writing, and why GDB needs to know which parts
of the address space hold NOR flash memory.
@quotation Note
Most of these erase and write commands leverage the fact that NOR flash
-chips consume target address space. They implicitly refer to the current
+chips consume target address space. They implicitly refer to the current
JTAG target, and map from an address in that target's address space
back to a flash bank.
@comment In May 2009, those mappings may fail if any bank associated
disabled first.
Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
and AT91SAM7 on-chip flash.
-@xref{flash protect}.
+@xref{flashprotect,,flash protect}.
-@anchor{flash erase_sector}
@deffn Command {flash erase_sector} num first last
Erase sectors in bank @var{num}, starting at sector @var{first}
up to and including @var{last}.
@end deffn
@comment no current checks for errors if fill blocks touch multiple banks!
-@anchor{flash write_bank}
@deffn Command {flash write_bank} num filename offset
Write the binary @file{filename} to flash bank @var{num},
starting at @var{offset} bytes from the beginning of the bank.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
-@anchor{flash write_image}
@deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
Write the image @file{filename} to the current target's flash bank(s).
+Only loadable sections from the image are written.
A relocation @var{offset} may be specified, in which case it is added
to the base address for each section in the image.
The file [@var{type}] can be specified
and possibly stale information.
@end deffn
-@anchor{flash protect}
+@anchor{flashprotect}
@deffn Command {flash protect} num first last (@option{on}|@option{off})
Enable (@option{on}) or disable (@option{off}) protection of flash sectors
in flash bank @var{num}, starting at sector @var{first}
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
-@anchor{Flash Driver List}
+@deffn Command {flash padded_value} num value
+Sets the default value used for padding any image sections, This should
+normally match the flash bank erased value. If not specified by this
+comamnd or the flash driver then it defaults to 0xff.
+@end deffn
+
+@anchor{program}
+@deffn Command {program} filename [verify] [reset] [exit] [offset]
+This is a helper script that simplifies using OpenOCD as a standalone
+programmer. The only required parameter is @option{filename}, the others are optional.
+@xref{Flash Programming}.
+@end deffn
+
+@anchor{flashdriverlist}
@section Flash Driver List
As noted above, the @command{flash bank} command requires a driver name,
and allows driver-specific options and behaviors.
Some drivers also activate driver-specific commands.
+@deffn {Flash Driver} virtual
+This is a special driver that maps a previously defined bank to another
+address. All bank settings will be copied from the master physical bank.
+
+The @var{virtual} driver defines one mandatory parameters,
+
+@itemize
+@item @var{master_bank} The bank that this virtual address refers to.
+@end itemize
+
+So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
+the flash bank defined at address 0x1fc00000. Any cmds executed on
+the virtual banks are actually performed on the physical banks.
+@example
+flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
+flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
+flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
+@end example
+@end deffn
+
@subsection External Flash
@deffn {Flash Driver} cfi
@c "cfi part_id" disabled
@end deffn
+@deffn {Flash Driver} lpcspifi
+@cindex NXP SPI Flash Interface
+@cindex SPIFI
+@cindex lpcspifi
+NXP's LPC43xx and LPC18xx families include a proprietary SPI
+Flash Interface (SPIFI) peripheral that can drive and provide
+memory mapped access to external SPI flash devices.
+
+The lpcspifi driver initializes this interface and provides
+program and erase functionality for these serial flash devices.
+Use of this driver @b{requires} a working area of at least 1kB
+to be configured on the target device; more than this will
+significantly reduce flash programming times.
+
+The setup command only requires the @var{base} parameter. All
+other parameters are ignored, and the flash size and layout
+are configured by the driver.
+
+@example
+flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
+@end example
+
+@end deffn
+
@deffn {Flash Driver} stmsmi
@cindex STMicroelectronics Serial Memory Interface
@cindex SMI
@end deffn
+@deffn {Flash Driver} mrvlqspi
+This driver supports QSPI flash controller of Marvell's Wireless
+Microcontroller platform.
+
+The flash size is autodetected based on the table of known JEDEC IDs
+hardcoded in the OpenOCD sources.
+
+@example
+flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
+@end example
+
+@end deffn
+
@subsection Internal Flash (Microcontrollers)
@deffn {Flash Driver} aduc702x
@end example
@end deffn
+@anchor{at91samd}
+@deffn {Flash Driver} at91samd
+@cindex at91samd
+
+@deffn Command {at91samd chip-erase}
+Issues a complete Flash erase via the Device Service Unit (DSU). This can be
+used to erase a chip back to its factory state and does not require the
+processor to be halted.
+@end deffn
+
+@deffn Command {at91samd set-security}
+Secures the Flash via the Set Security Bit (SSB) command. This prevents access
+to the Flash and can only be undone by using the chip-erase command which
+erases the Flash contents and turns off the security bit. Warning: at this
+time, openocd will not be able to communicate with a secured chip and it is
+therefore not possible to chip-erase it without using another tool.
+
+@example
+at91samd set-security enable
+@end example
+@end deffn
+
+@deffn Command {at91samd eeprom}
+Shows or sets the EEPROM emulation size configuration, stored in the User Row
+of the Flash. When setting, the EEPROM size must be specified in bytes and it
+must be one of the permitted sizes according to the datasheet. Settings are
+written immediately but only take effect on MCU reset. EEPROM emulation
+requires additional firmware support and the minumum EEPROM size may not be
+the same as the minimum that the hardware supports. Set the EEPROM size to 0
+in order to disable this feature.
+
+@example
+at91samd eeprom
+at91samd eeprom 1024
+@end example
+@end deffn
+
+@deffn Command {at91samd bootloader}
+Shows or sets the bootloader size configuration, stored in the User Row of the
+Flash. This is called the BOOTPROT region. When setting, the bootloader size
+must be specified in bytes and it must be one of the permitted sizes according
+to the datasheet. Settings are written immediately but only take effect on
+MCU reset. Setting the bootloader size to 0 disables bootloader protection.
+
+@example
+at91samd bootloader
+at91samd bootloader 16384
+@end example
+@end deffn
+
+@end deffn
+
@anchor{at91sam3}
@deffn {Flash Driver} at91sam3
@cindex at91sam3
chips are confirmed.}
The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
-have one flash bank. In all cases the flash banks are at
+have one flash bank. In all cases the flash banks are at
the following fixed locations:
@example
@itemize
@item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
-@item @emph{Bank Size:} 128K/64K Per flash bank
+@item @emph{Bank Size:} 128K/64K Per flash bank
@item @emph{Sectors:} 16 or 8 per bank
@item @emph{SectorSize:} 8K Per Sector
@item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
This driver uses the same cmd names/syntax as @xref{at91sam3}.
@end deffn
+@deffn {Flash Driver} at91sam4l
+@cindex at91sam4l
+All members of the AT91SAM4L microcontroller family from
+Atmel include internal flash and use ARM's Cortex-M4 core.
+This driver uses the same cmd names/syntax as @xref{at91sam3}.
+
+The AT91SAM4L driver adds some additional commands:
+@deffn Command {at91sam4l smap_reset_deassert}
+This command releases internal reset held by SMAP
+and prepares reset vector catch in case of reset halt.
+Command is used internally in event event reset-deassert-post.
+@end deffn
+@end deffn
+
@deffn {Flash Driver} at91sam7
All members of the AT91SAM7 microcontroller family from Atmel include
-internal flash and use ARM7TDMI cores. The driver automatically
+internal flash and use ARM7TDMI cores. The driver automatically
recognizes a number of these chips using the chip identification
register, and autoconfigures itself.
@deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
-bit for the processor. Each processor has a number of such bits,
+bit for the processor. Each processor has a number of such bits,
used for controlling features such as brownout detection (so they
are not truly general purpose).
@quotation Note
@comment - defines mass_erase ... pointless given flash_erase_address
@end deffn
+@deffn {Flash Driver} efm32
+All members of the EFM32 microcontroller family from Energy Micro include
+internal flash and use ARM Cortex M3 cores. The driver automatically recognizes
+a number of these chips using the chip identification register, and
+autoconfigures itself.
+@example
+flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
+@end example
+@emph{The current implementation is incomplete. Unprotecting flash pages is not
+supported.}
+@end deffn
+
@deffn {Flash Driver} lpc2000
-Most members of the LPC1700 and LPC2000 microcontroller families from NXP
-include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
+This is the driver to support internal flash of all members of the
+LPC11(x)00 and LPC1300 microcontroller families and most members of
+the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000 and LPC54100
+microcontroller families from NXP.
@quotation Note
There are LPC2000 devices which are not supported by the @var{lpc2000}
@item @var{variant} ... required, may be
@option{lpc2000_v1} (older LPC21xx and LPC22xx)
@option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
-or @option{lpc1700} (LPC175x and LPC176x)
+@option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
+@option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
+LPC43x[2357])
+@option{lpc800} (LPC8xx)
+@option{lpc1100} (LPC11(x)xx and LPC13xx)
+@option{lpc1500} (LPC15xx)
+@option{lpc54100} (LPC541xx)
+@option{lpc4000} (LPC40xx)
+or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
+LPC8xx, LPC13xx, LPC17xx and LPC40xx
@item @var{clock_kHz} ... the frequency, in kiloHertz,
at which the core is running
@item @option{calc_checksum} ... optional (but you probably want to provide this!),
@end deffn
@deffn {Flash Driver} ocl
-@emph{No idea what this is, other than using some arm7/arm9 core.}
+This driver is an implementation of the ``on chip flash loader''
+protocol proposed by Pavel Chromy.
+
+It is a minimalistic command-response protocol intended to be used
+over a DCC when communicating with an internal or external flash
+loader running from RAM. An example implementation for AT91SAM7x is
+available in @file{contrib/loaders/flash/at91sam7x/}.
@example
flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
@end deffn
@end deffn
-@deffn {Flash Driver} stellaris
-All members of the Stellaris LM3Sxxx microcontroller family from
-Texas Instruments
-include internal flash and use ARM Cortex M3 cores.
+@deffn {Flash Driver} psoc4
+All members of the PSoC 41xx/42xx microcontroller family from Cypress
+include internal flash and use ARM Cortex M0 cores.
The driver automatically recognizes a number of these chips using
the chip identification register, and autoconfigures itself.
+
+Note: Erased internal flash reads as 00.
+System ROM of PSoC 4 does not implement erase of a flash sector.
+
+@example
+flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
+@end example
+
+psoc4-specific commands
+@deffn Command {psoc4 flash_autoerase} num (on|off)
+Enables or disables autoerase mode for a flash bank.
+
+If flash_autoerase is off, use mass_erase before flash programming.
+Flash erase command fails if region to erase is not whole flash memory.
+
+If flash_autoerase is on, a sector is both erased and programmed in one
+system ROM call. Flash erase command is ignored.
+This mode is suitable for gdb load.
+
+The @var{num} parameter is a value shown by @command{flash banks}.
+@end deffn
+
+@deffn Command {psoc4 mass_erase} num
+Erases the contents of the flash memory, protection and security lock.
+
+The @var{num} parameter is a value shown by @command{flash banks}.
+@end deffn
+@end deffn
+
+@deffn {Flash Driver} stellaris
+All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
+families from Texas Instruments include internal flash. The driver
+automatically recognizes a number of these chips using the chip
+identification register, and autoconfigures itself.
@footnote{Currently there is a @command{stellaris mass_erase} command.
That seems pointless since the same effect can be had using the
standard @command{flash erase_address} command.}
@example
flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
@end example
-@end deffn
-@deffn Command {stellaris recover bank_id}
-Performs the @emph{Recovering a "Locked" Device} procedure to
-restore the flash specified by @var{bank_id} and its associated
-nonvolatile registers to their factory default values (erased).
-This is the only way to remove flash protection or re-enable
-debugging if that capability has been disabled.
+@deffn Command {stellaris recover}
+Performs the @emph{Recovering a "Locked" Device} procedure to restore
+the flash and its associated nonvolatile registers to their factory
+default values (erased). This is the only way to remove flash
+protection or re-enable debugging if that capability has been
+disabled.
Note that the final "power cycle the chip" step in this procedure
must be performed by hand, since OpenOCD can't do it.
applied to all of them.
@end quotation
@end deffn
+@end deffn
@deffn {Flash Driver} stm32f1x
-All members of the STM32f1x microcontroller family from ST Microelectronics
-include internal flash and use ARM Cortex M3 cores.
+All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
+from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
The driver automatically recognizes a number of these chips using
the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
@end example
+Note that some devices have been found that have a flash size register that contains
+an invalid value, to workaround this issue you can override the probed value used by
+the flash driver.
+
+@example
+flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
+@end example
+
If you have a target with dual flash banks then define the second bank
as per the following example.
@example
@end deffn
@deffn {Flash Driver} stm32f2x
-All members of the STM32f2x microcontroller family from ST Microelectronics
-include internal flash and use ARM Cortex M3 cores.
+All members of the STM32F2 and STM32F4 microcontroller families from ST Microelectronics
+include internal flash and use ARM Cortex-M3/M4 cores.
The driver automatically recognizes a number of these chips using
the chip identification register, and autoconfigures itself.
-@end deffn
-@deffn {Flash Driver} str7x
-All members of the STR7 microcontroller family from ST Microelectronics
-include internal flash and use ARM7TDMI cores.
-The @var{str7x} driver defines one mandatory parameter, @var{variant},
-which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
+Note that some devices have been found that have a flash size register that contains
+an invalid value, to workaround this issue you can override the probed value used by
+the flash driver.
@example
-flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
+flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
@end example
-@deffn Command {str7x disable_jtag} bank
-Activate the Debug/Readout protection mechanism
-for the specified flash bank.
+Some stm32f2x-specific commands are defined:
+
+@deffn Command {stm32f2x lock} num
+Locks the entire stm32 device.
+The @var{num} parameter is a value shown by @command{flash banks}.
+@end deffn
+
+@deffn Command {stm32f2x unlock} num
+Unlocks the entire stm32 device.
+The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@end deffn
-@deffn {Flash Driver} str9x
-Most members of the STR9 microcontroller family from ST Microelectronics
-include internal flash and use ARM966E cores.
-The str9 needs the flash controller to be configured using
-the @command{str9x flash_config} command prior to Flash programming.
+@deffn {Flash Driver} stm32lx
+All members of the STM32L microcontroller families from ST Microelectronics
+include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
+The driver automatically recognizes a number of these chips using
+the chip identification register, and autoconfigures itself.
+
+Note that some devices have been found that have a flash size register that contains
+an invalid value, to workaround this issue you can override the probed value used by
+the flash driver. If you use 0 as the bank base address, it tells the
+driver to autodetect the bank location assuming you're configuring the
+second bank.
@example
-flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
-str9x flash_config 0 4 2 0 0x80000
+flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
@end example
-@deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
-Configures the str9 flash controller.
-The @var{num} parameter is a value shown by @command{flash banks}.
+Some stm32lx-specific commands are defined:
-@itemize @bullet
-@item @var{bbsr} - Boot Bank Size register
-@item @var{nbbsr} - Non Boot Bank Size register
-@item @var{bbadr} - Boot Bank Start Address register
-@item @var{nbbadr} - Boot Bank Start Address register
-@end itemize
+@deffn Command {stm32lx mass_erase} num
+Mass erases the entire stm32lx device (all flash banks and EEPROM
+data). This is the only way to unlock a protected flash (unless RDP
+Level is 2 which can't be unlocked at all).
+The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
-
@end deffn
-@deffn {Flash Driver} tms470
-Most members of the TMS470 microcontroller family from Texas Instruments
+@deffn {Flash Driver} str7x
+All members of the STR7 microcontroller family from ST Microelectronics
include internal flash and use ARM7TDMI cores.
-This driver doesn't require the chip and bus width to be specified.
+The @var{str7x} driver defines one mandatory parameter, @var{variant},
+which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
-Some tms470-specific commands are defined:
+@example
+flash bank $_FLASHNAME str7x \
+ 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
+@end example
-@deffn Command {tms470 flash_keyset} key0 key1 key2 key3
-Saves programming keys in a register, to enable flash erase and write commands.
+@deffn Command {str7x disable_jtag} bank
+Activate the Debug/Readout protection mechanism
+for the specified flash bank.
@end deffn
-
-@deffn Command {tms470 osc_mhz} clock_mhz
-Reports the clock speed, which is used to calculate timings.
@end deffn
-@deffn Command {tms470 plldis} (0|1)
-Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
-the flash clock.
-@end deffn
-@end deffn
+@deffn {Flash Driver} str9x
+Most members of the STR9 microcontroller family from ST Microelectronics
+include internal flash and use ARM966E cores.
+The str9 needs the flash controller to be configured using
+the @command{str9x flash_config} command prior to Flash programming.
-@deffn {Flash Driver} virtual
-This is a special driver that maps a previously defined bank to another
-address. All bank settings will be copied from the master physical bank.
+@example
+flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
+str9x flash_config 0 4 2 0 0x80000
+@end example
-The @var{virtual} driver defines one mandatory parameters,
+@deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
+Configures the str9 flash controller.
+The @var{num} parameter is a value shown by @command{flash banks}.
-@itemize
-@item @var{master_bank} The bank that this virtual address refers to.
+@itemize @bullet
+@item @var{bbsr} - Boot Bank Size register
+@item @var{nbbsr} - Non Boot Bank Size register
+@item @var{bbadr} - Boot Bank Start Address register
+@item @var{nbbadr} - Boot Bank Start Address register
@end itemize
-
-So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
-the flash bank defined at address 0x1fc00000. Any cmds executed on
-the virtual banks are actually performed on the physical banks.
-@example
-flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
-flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
-flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
-@end example
@end deffn
-@deffn {Flash Driver} fm3
-All members of the FM3 microcontroller family from Fujitsu
-include internal flash and use ARM Cortex M3 cores.
-The @var{fm3} driver uses the @var{target} parameter to select the
-correct bank config, it can currently be one of the following:
-@code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
-@code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
-
-@example
-flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
-@end example
@end deffn
-@subsection str9xpec driver
+@deffn {Flash Driver} str9xpec
@cindex str9xpec
+Only use this driver for locking/unlocking the device or configuring the option bytes.
+Use the standard str9 driver for programming.
+Before using the flash commands the turbo mode must be enabled using the
+@command{str9xpec enable_turbo} command.
+
Here is some background info to help
you better understand how this driver works. OpenOCD has two flash drivers for
the str9:
has been locked. Halting the core is not required for the @option{str9xpec} driver
as mentioned above, just issue the commands above manually or from a telnet prompt.
-@deffn {Flash Driver} str9xpec
-Only use this driver for locking/unlocking the device or configuring the option bytes.
-Use the standard str9 driver for programming.
-Before using the flash commands the turbo mode must be enabled using the
-@command{str9xpec enable_turbo} command.
-
Several str9xpec-specific commands are defined:
@deffn Command {str9xpec disable_turbo} num
@end deffn
+@deffn {Flash Driver} tms470
+Most members of the TMS470 microcontroller family from Texas Instruments
+include internal flash and use ARM7TDMI cores.
+This driver doesn't require the chip and bus width to be specified.
+
+Some tms470-specific commands are defined:
-@section mFlash
+@deffn Command {tms470 flash_keyset} key0 key1 key2 key3
+Saves programming keys in a register, to enable flash erase and write commands.
+@end deffn
-@subsection mFlash Configuration
-@cindex mFlash Configuration
+@deffn Command {tms470 osc_mhz} clock_mhz
+Reports the clock speed, which is used to calculate timings.
+@end deffn
-@deffn {Config Command} {mflash bank} soc base RST_pin target
-Configures a mflash for @var{soc} host bank at
-address @var{base}.
-The pin number format depends on the host GPIO naming convention.
-Currently, the mflash driver supports s3c2440 and pxa270.
+@deffn Command {tms470 plldis} (0|1)
+Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
+the flash clock.
+@end deffn
+@end deffn
-Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
+@deffn {Flash Driver} fm3
+All members of the FM3 microcontroller family from Fujitsu
+include internal flash and use ARM Cortex M3 cores.
+The @var{fm3} driver uses the @var{target} parameter to select the
+correct bank config, it can currently be one of the following:
+@code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
+@code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
@example
-mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
+flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
@end example
+@end deffn
-Example for pxa270 mflash where @var{RST pin} is GPIO 43:
+@deffn {Flash Driver} sim3x
+All members of the SiM3 microcontroller family from Silicon Laboratories
+include internal flash and use ARM Cortex M3 cores. It supports both JTAG
+and SWD interface.
+The @var{sim3x} driver tries to probe the device to auto detect the MCU.
+If this failes, it will use the @var{size} parameter as the size of flash bank.
@example
-mflash bank $_FLASHNAME pxa270 0x08000000 43 0
+flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
@end example
-@end deffn
-@subsection mFlash commands
-@cindex mFlash commands
+There are 2 commands defined in the @var{sim3x} driver:
-@deffn Command {mflash config pll} frequency
-Configure mflash PLL.
-The @var{frequency} is the mflash input frequency, in Hz.
-Issuing this command will erase mflash's whole internal nand and write new pll.
-After this command, mflash needs power-on-reset for normal operation.
-If pll was newly configured, storage and boot(optional) info also need to be update.
+@deffn Command {sim3x mass_erase}
+Erases the complete flash. This is used to unlock the flash.
+And this command is only possible when using the SWD interface.
@end deffn
-@deffn Command {mflash config boot}
-Configure bootable option.
-If bootable option is set, mflash offer the first 8 sectors
-(4kB) for boot.
+@deffn Command {sim3x lock}
+Lock the flash. To unlock use the @command{sim3x mass_erase} command.
@end deffn
-
-@deffn Command {mflash config storage}
-Configure storage information.
-For the normal storage operation, this information must be
-written.
@end deffn
-@deffn Command {mflash dump} num filename offset size
-Dump @var{size} bytes, starting at @var{offset} bytes from the
-beginning of the bank @var{num}, to the file named @var{filename}.
+@deffn {Flash Driver} nrf51
+All members of the nRF51 microcontroller families from Nordic Semiconductor
+include internal flash and use ARM Cortex-M0 core.
+
+@example
+flash bank $_FLASHNAME nrf51 0 0x00000000 0 0 $_TARGETNAME
+@end example
+
+Some nrf51-specific commands are defined:
+
+@deffn Command {nrf51 mass_erase}
+Erases the contents of the code memory and user information
+configuration registers as well. It must be noted that this command
+works only for chips that do not have factory pre-programmed region 0
+code.
@end deffn
-@deffn Command {mflash probe}
-Probe mflash.
@end deffn
-@deffn Command {mflash write} num filename offset
-Write the binary file @var{filename} to mflash bank @var{num}, starting at
-@var{offset} bytes from the beginning of the bank.
+@deffn {Flash Driver} mdr
+This drivers handles the integrated NOR flash on Milandr Cortex-M
+based controllers. A known limitation is that the Info memory can't be
+read or verified as it's not memory mapped.
+
+@example
+flash bank <name> mdr <base> <size> \
+ 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
+@end example
+
+@itemize @bullet
+@item @var{type} - 0 for main memory, 1 for info memory
+@item @var{page_count} - total number of pages
+@item @var{sec_count} - number of sector per page count
+@end itemize
+
+Example usage:
+@example
+if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
+ flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
+ 0 0 $_TARGETNAME 1 1 4
+@} else @{
+ flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
+ 0 0 $_TARGETNAME 0 32 4
+@}
+@end example
@end deffn
-@node NAND Flash Commands
-@chapter NAND Flash Commands
+@section NAND Flash Commands
@cindex NAND
Compared to NOR or SPI flash, NAND devices are inexpensive
-and high density. Today's NAND chips, and multi-chip modules,
+and high density. Today's NAND chips, and multi-chip modules,
commonly hold multiple GigaBytes of data.
NAND chips consist of a number of ``erase blocks'' of a given
size (such as 128 KBytes), each of which is divided into a
-number of pages (of perhaps 512 or 2048 bytes each). Each
+number of pages (of perhaps 512 or 2048 bytes each). Each
page of a NAND flash has an ``out of band'' (OOB) area to hold
Error Correcting Code (ECC) and other metadata, usually 16 bytes
of OOB for every 512 bytes of page data.
One key characteristic of NAND flash is that its error rate
-is higher than that of NOR flash. In normal operation, that
-ECC is used to correct and detect errors. However, NAND
+is higher than that of NOR flash. In normal operation, that
+ECC is used to correct and detect errors. However, NAND
blocks can also wear out and become unusable; those blocks
-are then marked "bad". NAND chips are even shipped from the
-manufacturer with a few bad blocks. The highest density chips
+are then marked "bad". NAND chips are even shipped from the
+manufacturer with a few bad blocks. The highest density chips
use a technology (MLC) that wears out more quickly, so ECC
support is increasingly important as a way to detect blocks
that have begun to fail, and help to preserve data integrity
with techniques such as wear leveling.
-Software is used to manage the ECC. Some controllers don't
+Software is used to manage the ECC. Some controllers don't
support ECC directly; in those cases, software ECC is used.
Other controllers speed up the ECC calculations with hardware.
-Single-bit error correction hardware is routine. Controllers
+Single-bit error correction hardware is routine. Controllers
geared for newer MLC chips may correct 4 or more errors for
every 512 bytes of data.
You will need to make sure that any data you write using
-OpenOCD includes the apppropriate kind of ECC. For example,
+OpenOCD includes the apppropriate kind of ECC. For example,
that may mean passing the @code{oob_softecc} flag when
writing NAND data, or ensuring that the correct hardware
ECC mode is used.
to access that device.
@item Operate on the flash via @command{nand subcommand}
@* Often commands to manipulate the flash are typed by a human, or run
-via a script in some automated way. Common task include writing a
+via a script in some automated way. Common task include writing a
boot loader, operating system, or other data needed to initialize or
de-brick a board.
@end enumerate
Some larger devices will work, since they are actually multi-chip
modules with two smaller chips and individual chipselect lines.
-@anchor{NAND Configuration}
-@section NAND Configuration Commands
+@anchor{nandconfiguration}
+@subsection NAND Configuration Commands
@cindex NAND configuration
NAND chips must be declared in configuration scripts,
commands; see the controller-specific documentation.
@b{NOTE:} This command is not available after OpenOCD
-initialization has completed. Use it in board specific
+initialization has completed. Use it in board specific
configuration files, not interactively.
@itemize @bullet
@item @var{name} ... may be used to reference the NAND bank
-in most other NAND commands. A number is also available.
+in most other NAND commands. A number is also available.
@item @var{driver} ... identifies the NAND controller driver
associated with the NAND device being declared.
-@xref{NAND Driver List}.
+@xref{nanddriverlist,,NAND Driver List}.
@item @var{target} ... names the target used when issuing
commands to the NAND controller.
@comment Actually, it's currently a controller-specific parameter...
@item @var{configparams} ... controllers may support, or require,
-additional parameters. See the controller-specific documentation
+additional parameters. See the controller-specific documentation
for more information.
@end itemize
@end deffn
it with most other NAND commands.
@end deffn
-@section Erasing, Reading, Writing to NAND Flash
+@subsection Erasing, Reading, Writing to NAND Flash
@deffn Command {nand dump} num filename offset length [oob_option]
@cindex NAND reading
on the directory used to start the OpenOCD server.
The @var{offset} and @var{length} must be exact multiples of the
-device's page size. They describe a data region; the OOB data
+device's page size. They describe a data region; the OOB data
associated with each such page may also be accessed.
@b{NOTE:} At the time this text was written, no error correction
@cindex NAND writing
@cindex NAND programming
Writes binary data from the file into the specified NAND device,
-starting at the specified offset. Those pages should already
+starting at the specified offset. Those pages should already
have been erased; you can't change zero bits to one bits.
The @var{num} parameter is the value shown by @command{nand list}.
All data in the file will be written, assuming it doesn't run
past the end of the device.
Only full pages are written, and any extra space in the last
-page will be filled with 0xff bytes. (That includes OOB data,
+page will be filled with 0xff bytes. (That includes OOB data,
if that's being written.)
@b{NOTE:} At the time this text was written, bad blocks are
-ignored. That is, this routine will not skip bad blocks,
-but will instead try to write them. This can cause problems.
+ignored. That is, this routine will not skip bad blocks,
+but will instead try to write them. This can cause problems.
-Provide at most one @var{option} parameter. With some
+Provide at most one @var{option} parameter. With some
NAND drivers, the meanings of these parameters may change
if @command{nand raw_access} was used to disable hardware ECC.
@itemize @bullet
with hardware-computed ECC data.
@item @code{oob_only}
@*File has only raw OOB data, which is written to the OOB area.
-Each page's data area stays untouched. @i{This can be a dangerous
+Each page's data area stays untouched. @i{This can be a dangerous
option}, since it can invalidate the ECC data.
You may need to force raw access to use this mode.
@item @code{oob_raw}
@b{NOTE:} This will not work when the underlying NAND controller
driver's @code{write_page} routine must update the OOB with a
-hardward-computed ECC before the data is written. This limitation may
+hardward-computed ECC before the data is written. This limitation may
be removed in a future release.
@end deffn
-@section Other NAND commands
+@subsection Other NAND commands
@cindex NAND other commands
@deffn Command {nand check_bad_blocks} num [offset length]
Checks for manufacturer bad block markers on the specified NAND
-device. If no parameters are provided, checks the whole
+device. If no parameters are provided, checks the whole
device; otherwise, starts at the specified @var{offset} and
continues for @var{length} bytes.
Both of those values must be exact multiples of the device's
The @var{num} parameter is the value shown by @command{nand list}.
This flag is cleared (disabled) by default, but changing that
-value won't affect all NAND devices. The key factor is whether
+value won't affect all NAND devices. The key factor is whether
the underlying driver provides @code{read_page} or @code{write_page}
-methods. If it doesn't provide those methods, the setting of
+methods. If it doesn't provide those methods, the setting of
this flag is irrelevant; all access is effectively ``raw''.
When those methods exist, they are normally used when reading
data (@command{nand dump} or reading bad block markers) or
-writing it (@command{nand write}). However, enabling
+writing it (@command{nand write}). However, enabling
raw access (setting the flag) prevents use of those methods,
bypassing hardware ECC logic.
@i{This can be a dangerous option}, since writing blocks
with the wrong ECC data can cause them to be marked as bad.
@end deffn
-@anchor{NAND Driver List}
-@section NAND Driver List
+@anchor{nanddriverlist}
+@subsection NAND Driver List
As noted above, the @command{nand device} command allows
driver-specific options and behaviors.
Some controllers also activate controller-specific commands.
@deffn {NAND Driver} at91sam9
This driver handles the NAND controllers found on AT91SAM9 family chips from
-Atmel. It takes two extra parameters: address of the NAND chip;
+Atmel. It takes two extra parameters: address of the NAND chip;
address of the ECC controller.
@example
nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
@end example
AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
@code{read_page} methods are used to utilize the ECC hardware unless they are
-disabled by using the @command{nand raw_access} command. There are four
+disabled by using the @command{nand raw_access} command. There are four
additional commands that are needed to fully configure the AT91SAM9 NAND
-controller. Two are optional; most boards use the same wiring for ALE/CLE:
+controller. Two are optional; most boards use the same wiring for ALE/CLE:
@deffn Command {at91sam9 cle} num addr_line
-Configure the address line used for latching commands. The @var{num}
+Configure the address line used for latching commands. The @var{num}
parameter is the value shown by @command{nand list}.
@end deffn
@deffn Command {at91sam9 ale} num addr_line
-Configure the address line used for latching addresses. The @var{num}
+Configure the address line used for latching addresses. The @var{num}
parameter is the value shown by @command{nand list}.
@end deffn
For the next two commands, it is assumed that the pins have already been
properly configured for input or output.
@deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
-Configure the RDY/nBUSY input from the NAND device. The @var{num}
-parameter is the value shown by @command{nand list}. @var{pio_base_addr}
+Configure the RDY/nBUSY input from the NAND device. The @var{num}
+parameter is the value shown by @command{nand list}. @var{pio_base_addr}
is the base address of the PIO controller and @var{pin} is the pin number.
@end deffn
@deffn Command {at91sam9 ce} num pio_base_addr pin
-Configure the chip enable input to the NAND device. The @var{num}
-parameter is the value shown by @command{nand list}. @var{pio_base_addr}
+Configure the chip enable input to the NAND device. The @var{num}
+parameter is the value shown by @command{nand list}. @var{pio_base_addr}
is the base address of the PIO controller and @var{pin} is the pin number.
@end deffn
@end deffn
@deffn {NAND Driver} lpc3180
These controllers require an extra @command{nand device}
-parameter: the clock rate used by the controller.
+parameter: the clock rate used by the controller.
@deffn Command {lpc3180 select} num [mlc|slc]
Configures use of the MLC or SLC controller mode.
MLC implies use of hardware ECC.
@end deffn
At this writing, this driver includes @code{write_page}
-and @code{read_page} methods. Using @command{nand raw_access}
+and @code{read_page} methods. Using @command{nand raw_access}
to disable those methods will prevent use of hardware ECC
in the MLC controller mode, but won't change SLC behavior.
@end deffn
@deffn {NAND Driver} orion
These controllers require an extra @command{nand device}
-parameter: the address of the controller.
+parameter: the address of the controller.
@example
nand device orion 0xd8000000
@end example
change any behavior.
@end deffn
+@section mFlash
+
+@subsection mFlash Configuration
+@cindex mFlash Configuration
+
+@deffn {Config Command} {mflash bank} soc base RST_pin target
+Configures a mflash for @var{soc} host bank at
+address @var{base}.
+The pin number format depends on the host GPIO naming convention.
+Currently, the mflash driver supports s3c2440 and pxa270.
+
+Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
+
+@example
+mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
+@end example
+
+Example for pxa270 mflash where @var{RST pin} is GPIO 43:
+
+@example
+mflash bank $_FLASHNAME pxa270 0x08000000 43 0
+@end example
+@end deffn
+
+@subsection mFlash commands
+@cindex mFlash commands
+
+@deffn Command {mflash config pll} frequency
+Configure mflash PLL.
+The @var{frequency} is the mflash input frequency, in Hz.
+Issuing this command will erase mflash's whole internal nand and write new pll.
+After this command, mflash needs power-on-reset for normal operation.
+If pll was newly configured, storage and boot(optional) info also need to be update.
+@end deffn
+
+@deffn Command {mflash config boot}
+Configure bootable option.
+If bootable option is set, mflash offer the first 8 sectors
+(4kB) for boot.
+@end deffn
+
+@deffn Command {mflash config storage}
+Configure storage information.
+For the normal storage operation, this information must be
+written.
+@end deffn
+
+@deffn Command {mflash dump} num filename offset size
+Dump @var{size} bytes, starting at @var{offset} bytes from the
+beginning of the bank @var{num}, to the file named @var{filename}.
+@end deffn
+
+@deffn Command {mflash probe}
+Probe mflash.
+@end deffn
+
+@deffn Command {mflash write} num filename offset
+Write the binary file @var{filename} to mflash bank @var{num}, starting at
+@var{offset} bytes from the beginning of the bank.
+@end deffn
+
+@node Flash Programming
+@chapter Flash Programming
+
+OpenOCD implements numerous ways to program the target flash, whether internal or external.
+Programming can be acheived by either using GDB @ref{programmingusinggdb,,Programming using GDB},
+or using the cmds given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
+
+@*To simplify using the flash cmds directly a jimtcl script is available that handles the programming and verify stage.
+OpenOCD will program/verify/reset the target and optionally shutdown.
+
+The script is executed as follows and by default the following actions will be peformed.
+@enumerate
+@item 'init' is executed.
+@item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
+@item @code{flash write_image} is called to erase and write any flash using the filename given.
+@item @code{verify_image} is called if @option{verify} parameter is given.
+@item @code{reset run} is called if @option{reset} parameter is given.
+@item OpenOCD is shutdown if @option{exit} parameter is given.
+@end enumerate
+
+An example of usage is given below. @xref{program}.
+
+@example
+# program and verify using elf/hex/s19. verify and reset
+# are optional parameters
+openocd -f board/stm32f3discovery.cfg \
+ -c "program filename.elf verify reset exit"
+
+# binary files need the flash address passing
+openocd -f board/stm32f3discovery.cfg \
+ -c "program filename.bin exit 0x08000000"
+@end example
+
@node PLD/FPGA Commands
@chapter PLD/FPGA Commands
@cindex PLD
(@command{script} command and @command{target_name} configuration).
@end deffn
-@deffn Command shutdown
-Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
+@deffn Command shutdown [@option{error}]
+Close the OpenOCD daemon, disconnecting all clients (GDB, telnet,
+other). If option @option{error} is used, OpenOCD will return a
+non-zero exit code to the parent process.
@end deffn
-@anchor{debug_level}
+@anchor{debuglevel}
@deffn Command debug_level [n]
@cindex message level
Display debug level.
Add @var{directory} to the file/script search path.
@end deffn
-@anchor{Target State handling}
+@anchor{targetstatehandling}
@section Target State handling
@cindex reset
@cindex halt
shown earlier (@pxref{CPU Configuration}).
These commands, like many, implicitly refer to
a current target which is used to perform the
-various operations. The current target may be changed
+various operations. The current target may be changed
by using @command{targets} command with the name of the
target which should become current.
-@deffn Command reg [(number|name) [value]]
+@deffn Command reg [(number|name) [(value|'force')]]
Access a single register by @var{number} or by its @var{name}.
The target must generally be halted before access to CPU core
-registers is allowed. Depending on the hardware, some other
+registers is allowed. Depending on the hardware, some other
registers may be accessible while the target is running.
@emph{With no arguments}:
are flagged as such.
@emph{With number/name}: display that register's value.
+Use @var{force} argument to read directly from the target,
+bypassing any internal cache.
@emph{With both number/name and value}: set register's value.
Writes may be held in a writeback cache internal to OpenOCD,
so that setting the value marks the register as dirty instead
-of immediately flushing that value. Resuming CPU execution
+of immediately flushing that value. Resuming CPU execution
(including by single stepping) or otherwise activating the
relevant module will flush such values.
@deffnx Command wait_halt [ms]
The @command{halt} command first sends a halt request to the target,
which @command{wait_halt} doesn't.
-Otherwise these behave the same: wait up to @var{ms} milliseconds,
+Otherwise these behave the same: wait up to @var{ms} milliseconds,
or 5 seconds if there is no parameter, for the target to halt
(and enter debug mode).
Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
power mode by gating the core clock;
but the core clock is needed to detect JTAG clock transitions.
-One partial workaround uses adaptive clocking: when the core is
+One partial workaround uses adaptive clocking: when the core is
interrupted the operation completes, then JTAG clocks are accepted
at least until the interrupt handler completes.
However, this workaround is often unusable since the processor, board,
or the optional @var{address} if it is provided.
@end deffn
-@anchor{Reset Command}
+@anchor{resetcommand}
@deffn Command reset
@deffnx Command {reset run}
@deffnx Command {reset halt}
@emph{No description provided.}
@end deffn
-@deffn Command meminfo
+@deffn Command meminfo
Display available RAM memory on OpenOCD host.
Used in OpenOCD regression testing scripts.
@end deffn
Removes all data in the file @file{filename}.
@end deffn
-@anchor{Memory access}
+@anchor{memoryaccess}
@section Memory access commands
@cindex memory access
@var{addr} is interpreted as a physical address.
@end deffn
-
-@anchor{Image access}
+@anchor{imageaccess}
@section Image loading commands
@cindex image loading
@cindex image dumping
-@anchor{dump_image}
@deffn Command {dump_image} filename address size
Dump @var{size} bytes of target memory starting at @var{address} to the
binary file named @var{filename}.
host), storing the image in memory and uploading the image to the target
can be a way to upload e.g. multiple debug sessions when the binary does not change.
Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
-memory, i.e. does not affect target. This approach is also useful when profiling
+memory, i.e. does not affect target. This approach is also useful when profiling
target programming performance as I/O and target programming can easily be profiled
separately.
@end deffn
-@anchor{load_image}
@deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
Load image from file @var{filename} to target memory offset by @var{address} from its load address.
The file format may optionally be specified
proc load_image_bin @{fname foffset address length @} @{
# Load data from fname filename at foffset offset to
# target at address. Load at most length bytes.
- load_image $fname [expr $address - $foffset] bin $address $length
+ load_image $fname [expr $address - $foffset] bin \
+ $address $length
@}
@end example
@end deffn
This is a software breakpoint, unless @option{hw} is specified
in which case it will be a hardware breakpoint.
-(@xref{arm9 vector_catch}, or @pxref{xscale vector_catch},
+(@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
for similar mechanisms that do not consume hardware breakpoints.)
@end deffn
the @option{r} or @option{w} parameter is provided,
defining it as respectively a read or write watchpoint.
If a @var{value} is provided, that value is used when determining if
-the watchpoint should trigger. The value may be first be masked
+the watchpoint should trigger. The value may be first be masked
using @var{mask} to mark ``don't care'' fields.
@end deffn
@section Misc Commands
@cindex profiling
-@deffn Command {profile} seconds filename
+@deffn Command {profile} seconds filename [start end]
Profiling samples the CPU's program counter as quickly as possible,
which is useful for non-intrusive stochastic profiling.
-Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
+Saves up to 10000 samples in @file{filename} using ``gmon.out''
+format. Optional @option{start} and @option{end} parameters allow to
+limit the address range.
@end deffn
@deffn Command {version}
Some of those operations don't fit well in that framework, so they are
exposed here as architecture or implementation (core) specific commands.
-@anchor{ARM Hardware Tracing}
+@anchor{armhardwaretracing}
@section ARM Hardware Tracing
@cindex tracing
@cindex ETM
@item
If the CPU doesn't provide an external interface, it probably
has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
-dedicated SRAM. 4KBytes is one common ETB size.
+dedicated SRAM. 4KBytes is one common ETB size.
Configuring an ETM coupled only to an ETB belongs in the CPU-specific
(target) configuration file, since it works the same on all boards.
@end itemize
shared with eventual Nexus-style trace module support.
At this writing (November 2009) only ARM7, ARM9, and ARM11 support
-for ETM modules is available. The code should be able to
+for ETM modules is available. The code should be able to
work with some newer cores; but not all of them support
this original style of JTAG access.
@end quotation
@deffn {Config Command} {etm config} target width mode clocking driver
Declares the ETM associated with @var{target}, and associates it
-with a given trace port @var{driver}. @xref{Trace Port Drivers}.
+with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
Several of the parameters must reflect the trace port capabilities,
which are a function of silicon capabilties (exposed later
@option{address} (save addresses),
@option{all} (save data and addresses)
@item @var{context_id_bits} ... 0, 8, 16, or 32
-@item @var{cycle_accurate} ... @option{enable} or @option{disable}
+@item @var{cycle_accurate} ... @option{enable} or @option{disable}
cycle-accurate instruction tracing.
Before ETMv3, enabling this causes much extra data to be recorded.
-@item @var{branch_output} ... @option{enable} or @option{disable}.
+@item @var{branch_output} ... @option{enable} or @option{disable}.
Disable this unless you need to try reconstructing the instruction
trace stream without an image of the code.
@end itemize
For the definitions of these registers, read ARM publication
@emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
Be aware that most of the relevant registers are write-only,
-and that ETM resources are limited. There are only a handful
+and that ETM resources are limited. There are only a handful
of address comparators, data comparators, counters, and so on.
Examples of scenarios you might arrange to trace include:
@itemize
@item Code flow within a function, @emph{excluding} subroutines
-it calls. Use address range comparators to enable tracing
+it calls. Use address range comparators to enable tracing
for instruction access within that function's body.
@item Code flow within a function, @emph{including} subroutines
-it calls. Use the sequencer and address comparators to activate
+it calls. Use the sequencer and address comparators to activate
tracing on an ``entered function'' state, then deactivate it by
exiting that state when the function's exit code is invoked.
@item Code flow starting at the fifth invocation of a function,
Stops trace data collection.
@end deffn
-@anchor{Trace Port Drivers}
+@anchor{traceportdrivers}
@subsection Trace Port Drivers
To use an ETM trace port it must be associated with a driver.
@deffn {Trace Port Driver} oocd_trace
This driver isn't available unless OpenOCD was explicitly configured
-with the @option{--enable-oocd_trace} option. You probably don't want
+with the @option{--enable-oocd_trace} option. You probably don't want
to configure it unless you've built the appropriate prototype hardware;
it's @emph{proof-of-concept} software.
with OpenOCD rev. 60, and requires a few bytes of working area.
@end deffn
-@anchor{arm7_9 fast_memory_access}
@deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
Displays the value of the flag controlling use of memory writes and reads
that don't check completion of the operation.
integer processors.
Such cores include the ARM920T, ARM926EJ-S, and ARM966.
-@c 9-june-2009: tried this on arm920t, it didn't work.
+@c 9-june-2009: tried this on arm920t, it didn't work.
@c no-params always lists nothing caught, and that's how it acts.
-@c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
+@c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
@c versions have different rules about when they commit writes.
-@anchor{arm9 vector_catch}
+@anchor{arm9vectorcatch}
@deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
@cindex vector_catch
Vector Catch hardware provides a sort of dedicated breakpoint
Alternatively, you may choose to keep some or all of the mini-IC
vector table entries synced with those written to memory by your
-system software. The mini-IC can not be modified while the processor
+system software. The mini-IC can not be modified while the processor
is executing, but for each vector table entry not previously defined
using the @code{xscale vector_table} command, OpenOCD will copy the
value from memory to the mini-IC every time execution resumes from a
-halt. This is done for both high and low vector tables (although the
+halt. This is done for both high and low vector tables (although the
table not in use may not be mapped to valid memory, and in this case
-that copy operation will silently fail). This means that you will
+that copy operation will silently fail). This means that you will
need to briefly halt execution at some strategic point during system
start-up; e.g., after the software has initialized the vector table,
-but before exceptions are enabled. A breakpoint can be used to
+but before exceptions are enabled. A breakpoint can be used to
accomplish this once the appropriate location in the start-up code has
-been identified. A watchpoint over the vector table region is helpful
-in finding the location if you're not sure. Note that the same
+been identified. A watchpoint over the vector table region is helpful
+in finding the location if you're not sure. Note that the same
situation exists any time the vector table is modified by the system
software.
The debug handler must be placed somewhere in the address space using
-the @code{xscale debug_handler} command. The allowed locations for the
+the @code{xscale debug_handler} command. The allowed locations for the
debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
0xfffff800). The default value is 0xfe000800.
XScale has resources to support two hardware breakpoints and two
-watchpoints. However, the following restrictions on watchpoint
+watchpoints. However, the following restrictions on watchpoint
functionality apply: (1) the value and mask arguments to the @code{wp}
command are not supported, (2) the watchpoint length must be a
power of two and not less than four, and can not be greater than the
watchpoint address, and (3) a watchpoint with a length greater than
-four consumes all the watchpoint hardware resources. This means that
+four consumes all the watchpoint hardware resources. This means that
at any one time, you can have enabled either two watchpoints with a
length of four, or one watchpoint with a length greater than four.
@option{mem}, or @option{builder}.
@end deffn
-@anchor{xscale vector_catch}
+@anchor{xscalevectorcatch}
@deffn Command {xscale vector_catch} [mask]
@cindex vector_catch
Display a bitmask showing the hardware vectors to catch.
@end example
@end deffn
-@anchor{xscale vector_table}
@deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
@cindex vector_table
@cindex Debug Access Port
@cindex DAP
These commands are specific to ARM architecture v7 Debug Access Port (DAP),
-included on Cortex-M3 and Cortex-A8 systems.
+included on Cortex-M and Cortex-A systems.
They are available in addition to other core-specific commands that may be available.
@deffn Command {dap apid} [num]
If @var{value} is defined, first assigns that.
@end deffn
-@subsection Cortex-M3 specific commands
-@cindex Cortex-M3
+@deffn Command {dap apcsw} [0 / 1]
+fix CSW_SPROT from register AP_REG_CSW on selected dap.
+Defaulting to 0.
+@end deffn
+
+@subsection ARMv7-M specific commands
+@cindex tracing
+@cindex SWO
+@cindex SWV
+@cindex TPIU
+@cindex ITM
+@cindex ETM
+
+@deffn Command {tpiu config} (@option{disable} | ((@option{external} | @option{internal @var{filename}}) @
+ (@option{sync @var{port_width}} | ((@option{manchester} | @option{uart}) @var{formatter_enable})) @
+ @var{TRACECLKIN_freq} [@var{trace_freq}]))
+
+ARMv7-M architecture provides several modules to generate debugging
+information internally (ITM, DWT and ETM). Their output is directed
+through TPIU to be captured externally either on an SWO pin (this
+configuration is called SWV) or on a synchronous parallel trace port.
+
+This command configures the TPIU module of the target and, if internal
+capture mode is selected, starts to capture trace output by using the
+debugger adapter features.
+
+Some targets require additional actions to be performed in the
+@b{trace-config} handler for trace port to be activated.
+
+Command options:
+@itemize @minus
+@item @option{disable} disable TPIU handling;
+@item @option{external} configure TPIU to let user capture trace
+output externally (with an additional UART or logic analyzer hardware);
+@item @option{internal @var{filename}} configure TPIU and debug adapter to
+gather trace data and append it to @var{filename} (which can be
+either a regular file or a named pipe);
+@item @option{sync @var{port_width}} use synchronous parallel trace output
+mode, and set port width to @var{port_width};
+@item @option{manchester} use asynchronous SWO mode with Manchester
+coding;
+@item @option{uart} use asynchronous SWO mode with NRZ (same as
+regular UART 8N1) coding;
+@item @var{formatter_enable} is @option{on} or @option{off} to enable
+or disable TPIU formatter which needs to be used when both ITM and ETM
+data is to be output via SWO;
+@item @var{TRACECLKIN_freq} this should be specified to match target's
+current TRACECLKIN frequency (usually the same as HCLK);
+@item @var{trace_freq} trace port frequency. Can be omitted in
+internal mode to let the adapter driver select the maximum supported
+rate automatically.
+@end itemize
+
+Example usage:
+@enumerate
+@item STM32L152 board is programmed with an application that configures
+PLL to provide core clock with 24MHz frequency; to use ITM output it's
+enough to:
+@example
+#include <libopencm3/cm3/itm.h>
+ ...
+ ITM_STIM8(0) = c;
+ ...
+@end example
+(the most obvious way is to use the first stimulus port for printf,
+for that this ITM_STIM8 assignment can be used inside _write(); to make it
+blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
+ITM_STIM_FIFOREADY));});
+@item An FT2232H UART is connected to the SWO pin of the board;
+@item Commands to configure UART for 12MHz baud rate:
+@example
+$ setserial /dev/ttyUSB1 spd_cust divisor 5
+$ stty -F /dev/ttyUSB1 38400
+@end example
+(FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
+baud with our custom divisor to get 12MHz)
+@item @code{itmdump -f /dev/ttyUSB1 -d1}
+@item OpenOCD invocation line:
+@example
+openocd -f interface/stlink-v2-1.cfg \
+ -c "transport select hla_swd" \
+ -f target/stm32l1.cfg \
+ -c "tpiu config external uart off 24000000 12000000"
+@end example
+@end enumerate
+@end deffn
+
+@deffn Command {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
+Enable or disable trace output for ITM stimulus @var{port} (counting
+from 0). Port 0 is enabled on target creation automatically.
+@end deffn
+
+@deffn Command {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
+Enable or disable trace output for all ITM stimulus ports.
+@end deffn
-@deffn Command {cortex_m3 maskisr} (@option{auto}|@option{on}|@option{off})
+@subsection Cortex-M specific commands
+@cindex Cortex-M
+
+@deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
Control masking (disabling) interrupts during target step/resume.
The @option{auto} option handles interrupts during stepping a way they get
Default is @option{auto}.
@end deffn
-@deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
+@deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
@cindex vector_catch
Vector Catch hardware provides dedicated breakpoints
for certain hardware events.
This finishes by listing the current vector catch configuration.
@end deffn
-@deffn Command {cortex_m3 reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
+@deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
Control reset handling. The default @option{srst} is to use srst if fitted,
otherwise fallback to @option{vectreset}.
@itemize @minus
@item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
@item @option{vectreset} use NVIC VECTRESET to reset system.
@end itemize
-Using @option{vectreset} is a safe option for all current Cortex-M3 cores.
+Using @option{vectreset} is a safe option for all current Cortex-M cores.
This however has the disadvantage of only resetting the core, all peripherals
are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
the peripherals.
-@xref{Target Events}.
+@xref{targetevents,,Target Events}.
@end deffn
-@anchor{Software Debug Messages and Tracing}
+@section Intel Architecture
+
+Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
+(Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
+Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
+software debug and the CLTAP is used for SoC level operations.
+Useful docs are here: https://communities.intel.com/community/makers/documentation
+@itemize
+@item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
+@item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
+@item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
+@end itemize
+
+@subsection x86 32-bit specific commands
+The three main address spaces for x86 are memory, I/O and configuration space.
+These commands allow a user to read and write to the 64Kbyte I/O address space.
+
+@deffn Command {x86_32 idw} address
+Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
+@end deffn
+
+@deffn Command {x86_32 idh} address
+Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
+@end deffn
+
+@deffn Command {x86_32 idb} address
+Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
+@end deffn
+
+@deffn Command {x86_32 iww} address
+Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
+@end deffn
+
+@deffn Command {x86_32 iwh} address
+Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
+@end deffn
+
+@deffn Command {x86_32 iwb} address
+Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
+@end deffn
+
+@section OpenRISC Architecture
+
+The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
+configured with any of the TAP / Debug Unit available.
+
+@subsection TAP and Debug Unit selection commands
+@deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
+Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
+@end deffn
+@deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
+Select between the Advanced Debug Interface and the classic one.
+
+An option can be passed as a second argument to the debug unit.
+
+When using the Advanced Debug Interface, option = 1 means the RTL core is
+configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
+between bytes while doing read or write bursts.
+@end deffn
+
+@subsection Registers commands
+@deffn Command {addreg} [name] [address] [feature] [reg_group]
+Add a new register in the cpu register list. This register will be
+included in the generated target descriptor file.
+
+@strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
+
+@strong{[reg_group]} can be anything. The default register list defines "system",
+ "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
+ and "timer" groups.
+
+@emph{example:}
+@example
+addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
+@end example
+
+
+@end deffn
+@deffn Command {readgroup} (@option{group})
+Display all registers in @emph{group}.
+
+@emph{group} can be "system",
+ "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
+ "timer" or any new group created with addreg command.
+@end deffn
+
+@anchor{softwaredebugmessagesandtracing}
@section Software Debug Messages and Tracing
@cindex Linux-ARM DCC support
@cindex tracing
a lighter weight mechanism using only the DCC channel.
Currently @command{target_request debugmsgs}
-is supported only for @option{arm7_9} and @option{cortex_m3} cores.
+is supported only for @option{arm7_9} and @option{cortex_m} cores.
These messages are received as part of target polling, so
you need to have @command{poll on} active to receive them.
They are intrusive in that they will affect program execution
-times. If that is a problem, @pxref{ARM Hardware Tracing}.
+times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
See @file{libdcc} in the contrib dir for more details.
In addition to sending strings, characters, and
With a numeric @var{identifier} parameter, creates a new a trace point counter
and associates it with that identifier.
-@emph{Important:} The identifier and the trace point number
+@emph{Important:} The identifier and the trace point number
are not related except by this command.
These trace point numbers always start at zero (from server startup,
or after @command{trace point clear}) and count up from there.
@chapter JTAG Commands
@cindex JTAG Commands
Most general purpose JTAG commands have been presented earlier.
-(@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
+(@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
Lower level JTAG commands, as presented here,
may be needed to work with targets which require special
attention during operations such as reset or initialization.
For example, a 38 bit number might be specified as one
field of 32 bits then one of 6 bits.
@emph{For portability, never pass fields which are more
-than 32 bits long. Many OpenOCD implementations do not
+than 32 bits long. Many OpenOCD implementations do not
support 64-bit (or larger) integer values.}
All TAPs other than @var{tap} must be in BYPASS mode.
@deffn Command {verify_ircapture} (@option{enable}|@option{disable})
Verify values captured during @sc{ircapture} and returned
-during IR scans. Default is enabled, but this can be
+during IR scans. Default is enabled, but this can be
overridden by @command{verify_jtag}.
This flag is ignored when validating JTAG chain configuration.
@end deffn
@deffn Command {verify_jtag} (@option{enable}|@option{disable})
Enables verification of DR and IR scans, to help detect
-programming errors. For IR scans, @command{verify_ircapture}
+programming errors. For IR scans, @command{verify_ircapture}
must also be enabled.
Default is enabled.
@end deffn
Note that only six of those states are fully ``stable'' in the
face of TMS fixed (low except for @sc{reset})
-and a free-running JTAG clock. For all the
+and a free-running JTAG clock. For all the
others, the next TCK transition changes to a new state.
@itemize @bullet
@item From @sc{drshift} and @sc{irshift}, clock transitions will
-produce side effects by changing register contents. The values
+produce side effects by changing register contents. The values
to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
may not be as expected.
@item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
probably will not be usable with other XSVF tools.
+@node Utility Commands
+@chapter Utility Commands
+@cindex Utility Commands
+
+@section RAM testing
+@cindex RAM testing
+
+There is often a need to stress-test random access memory (RAM) for
+errors. OpenOCD comes with a Tcl implementation of well-known memory
+testing procedures allowing the detection of all sorts of issues with
+electrical wiring, defective chips, PCB layout and other common
+hardware problems.
+
+To use them, you usually need to initialise your RAM controller first;
+consult your SoC's documentation to get the recommended list of
+register operations and translate them to the corresponding
+@command{mww}/@command{mwb} commands.
+
+Load the memory testing functions with
+
+@example
+source [find tools/memtest.tcl]
+@end example
+
+to get access to the following facilities:
+
+@deffn Command {memTestDataBus} address
+Test the data bus wiring in a memory region by performing a walking
+1's test at a fixed address within that region.
+@end deffn
+
+@deffn Command {memTestAddressBus} baseaddress size
+Perform a walking 1's test on the relevant bits of the address and
+check for aliasing. This test will find single-bit address failures
+such as stuck-high, stuck-low, and shorted pins.
+@end deffn
+
+@deffn Command {memTestDevice} baseaddress size
+Test the integrity of a physical memory device by performing an
+increment/decrement test over the entire region. In the process every
+storage bit in the device is tested as zero and as one.
+@end deffn
+
+@deffn Command {runAllMemTests} baseaddress size
+Run all of the above tests over a specified memory region.
+@end deffn
+
+@section Firmware recovery helpers
+@cindex Firmware recovery
+
+OpenOCD includes an easy-to-use script to facilitate mass-market
+devices recovery with JTAG.
+
+For quickstart instructions run:
+@example
+openocd -f tools/firmware-recovery.tcl -c firmware_help
+@end example
+
@node TFTP
@chapter TFTP
@cindex TFTP
-If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
+If OpenOCD runs on an embedded host (as ZY1000 does), then TFTP can
be used to access files on PCs (either the developer's PC or some other PC).
The way this works on the ZY1000 is to prefix a filename by
@node GDB and OpenOCD
@chapter GDB and OpenOCD
@cindex GDB
-OpenOCD complies with the remote gdbserver protocol, and as such can be used
+OpenOCD complies with the remote gdbserver protocol and, as such, can be used
to debug remote targets.
Setting up GDB to work with OpenOCD can involve several components:
@itemize
@item The OpenOCD server support for GDB may need to be configured.
-@xref{GDB Configuration}.
+@xref{gdbconfiguration,,GDB Configuration}.
@item GDB's support for OpenOCD may need configuration,
as shown in this chapter.
@item If you have a GUI environment like Eclipse,
@end itemize
Of course, the version of GDB you use will need to be one which has
-been built to know about the target CPU you're using. It's probably
-part of the tool chain you're using. For example, if you are doing
+been built to know about the target CPU you're using. It's probably
+part of the tool chain you're using. For example, if you are doing
cross-development for ARM on an x86 PC, instead of using the native
x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
if that's the tool chain used to compile your code.
-@anchor{Connecting to GDB}
@section Connecting to GDB
@cindex Connecting to GDB
Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
target remote localhost:3333
@end example
This would cause GDB to connect to the gdbserver on the local pc using port 3333.
+
+It is also possible to use the GDB extended remote protocol as follows:
+@example
+target extended-remote localhost:3333
+@end example
@item
A pipe connection is typically started as follows:
@example
With the remote protocol, GDB sessions start a little differently
than they do when you're debugging locally.
-Here's an examples showing how to start a debug session with a
+Here's an example showing how to start a debug session with a
small ARM program.
In this case the program was linked to be loaded into SRAM on a Cortex-M3.
Most programs would be written into flash (address 0) and run from there.
@end example
With that particular hardware (Cortex-M3) the hardware breakpoints
-only work for code running from flash memory. Most other ARM systems
+only work for code running from flash memory. Most other ARM systems
do not have such restrictions.
Another example of useful GDB configuration came from a user who
@example
define hook-step
-mon cortex_m3 maskisr on
+mon cortex_m maskisr on
end
define hookpost-step
-mon cortex_m3 maskisr off
+mon cortex_m maskisr off
end
@end example
@section Programming using GDB
@cindex Programming using GDB
+@anchor{programmingusinggdb}
By default the target memory map is sent to GDB. This can be disabled by
the following OpenOCD configuration option:
Informing GDB of the memory map of the target will enable GDB to protect any
flash areas of the target and use hardware breakpoints by default. This means
that the OpenOCD option @command{gdb_breakpoint_override} is not required when
-using a memory map. @xref{gdb_breakpoint_override}.
+using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
-To view the configured memory map in GDB, use the GDB command @option{info mem}
+To view the configured memory map in GDB, use the GDB command @option{info mem}.
All other unassigned addresses within GDB are treated as RAM.
GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
To verify any flash programming the GDB command @option{compare-sections}
can be used.
-@anchor{Using openocd SMP with GDB}
-@section Using openocd SMP with GDB
+@anchor{usingopenocdsmpwithgdb}
+@section Using OpenOCD SMP with GDB
@cindex SMP
For SMP support following GDB serial protocol packet have been defined :
@itemize @bullet
OpenOCD implements :
@itemize @bullet
@item @option{jc} packet for reading core id displayed by
-GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
+GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
@option{E01} for target not smp.
-@item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
-(core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
+@item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
+(core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
for target not smp or @option{OK} on success.
@end itemize
#jc packet is sent and result is affected in $
@end example
-@item by the usage of GDB maintenance command as described in following example (2
-cpus in SMP with core id 0 and 1 @pxref{Define CPU targets working in SMP}).
+@item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
+core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
@example
# toggle0 : force display of coreid 0
@end example
@end itemize
+@section RTOS Support
+@cindex RTOS Support
+@anchor{gdbrtossupport}
+
+OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
+It can be enabled by passing @option{-rtos} arg to the target @xref{rtostype,,RTOS Type}.
+
+@* An example setup is below:
+
+@example
+$_TARGETNAME configure -rtos auto
+@end example
+
+This will attempt to auto detect the RTOS within your application.
+
+Currently supported rtos's include:
+@itemize @bullet
+@item @option{eCos}
+@item @option{ThreadX}
+@item @option{FreeRTOS}
+@item @option{linux}
+@item @option{ChibiOS}
+@item @option{embKernel}
+@item @option{mqx}
+@end itemize
+
+@quotation Note
+Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
+be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
+@end quotation
+
+@table @code
+@item eCos symbols
+Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
+@item ThreadX symbols
+_tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
+@item FreeRTOS symbols
+@raggedright
+pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
+pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
+uxCurrentNumberOfTasks, uxTopUsedPriority.
+@end raggedright
+@item linux symbols
+init_task.
+@item ChibiOS symbols
+rlist, ch_debug, chSysInit.
+@item embKernel symbols
+Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
+Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
+@item mqx symbols
+_mqx_kernel_data, MQX_init_struct.
+@end table
+
+For most RTOS supported the above symbols will be exported by default. However for
+some, eg. FreeRTOS, extra steps must be taken.
+
+These RTOSes may require additional OpenOCD-specific file to be linked
+along with the project:
+
+@table @code
+@item FreeRTOS
+contrib/rtos-helpers/FreeRTOS-openocd.c
+@end table
@node Tcl Scripting API
@chapter Tcl Scripting API
@cindex Tcl scripts
@section API rules
-The commands are stateless. E.g. the telnet command line has a concept
-of currently active target, the Tcl API proc's take this sort of state
-information as an argument to each proc.
+Tcl commands are stateless; e.g. the @command{telnet} command has
+a concept of currently active target, the Tcl API proc's take this sort
+of state information as an argument to each proc.
There are three main types of return values: single value, name value
pair list and lists.
Name value pair. The proc 'foo' below returns a name/value pair
list.
-@verbatim
-
- > set foo(me) Duane
- > set foo(you) Oyvind
- > set foo(mouse) Micky
- > set foo(duck) Donald
+@example
+> set foo(me) Duane
+> set foo(you) Oyvind
+> set foo(mouse) Micky
+> set foo(duck) Donald
+@end example
If one does this:
- > set foo
+@example
+> set foo
+@end example
The result is:
- me Duane you Oyvind mouse Micky duck Donald
+@example
+me Duane you Oyvind mouse Micky duck Donald
+@end example
Thus, to get the names of the associative array is easy:
- foreach { name value } [set foo] {
- puts "Name: $name, Value: $value"
- }
+@verbatim
+foreach { name value } [set foo] {
+ puts "Name: $name, Value: $value"
+}
@end verbatim
-Lists returned must be relatively small. Otherwise a range
+Lists returned should be relatively small. Otherwise, a range
should be passed in to the proc in question.
@section Internal low-level Commands
-By low-level, the intent is a human would not directly use these commands.
+By "low-level," we mean commands that a human would typically not
+invoke directly.
-Low-level commands are (should be) prefixed with "ocd_", e.g.
+Some low-level commands need to be prefixed with "ocd_"; e.g.
@command{ocd_flash_banks}
-is the low level API upon which @command{flash banks} is implemented.
+is the low-level API upon which @command{flash banks} is implemented.
@itemize @bullet
@item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
@item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
Return information about the flash banks
+
+@item @b{capture} <@var{command}>
+
+Run <@var{command}> and return full log output that was produced during
+its execution. Example:
+
+@example
+> capture "reset init"
+@end example
+
@end itemize
OpenOCD commands can consist of two words, e.g. "flash banks". The
@item @b{cygwin} Running under Cygwin
@item @b{darwin} Darwin (Mac-OS) is the underlying operating sytem.
@item @b{freebsd} Running under FreeBSD
+@item @b{openbsd} Running under OpenBSD
+@item @b{netbsd} Running under NetBSD
@item @b{linux} Linux is the underlying operating sytem
@item @b{mingw32} Running under MingW32
@item @b{winxx} Built using Microsoft Visual Studio
+@item @b{ecos} Running under eCos
@item @b{other} Unknown, none of the above.
@end itemize
is jim, not real tcl).
@end quotation
+@section Tcl RPC server
+@cindex RPC
+
+OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
+commands and receive the results.
+
+To access it, your application needs to connect to a configured TCP port
+(see @command{tcl_port}). Then it can pass any string to the
+interpreter terminating it with @code{0x1a} and wait for the return
+value (it will be terminated with @code{0x1a} as well). This can be
+repeated as many times as desired without reopening the connection.
+
+Remember that most of the OpenOCD commands need to be prefixed with
+@code{ocd_} to get the results back. Sometimes you might also need the
+@command{capture} command.
+
+See @file{contrib/rpc_examples/} for specific client implementations.
+
+@section Tcl RPC server notifications
+@cindex RPC Notifications
+
+Notifications are sent asynchronously to other commands being executed over
+the RPC server, so the port must be polled continuously.
+
+Target event, state and reset notifications are emitted as Tcl associative arrays
+in the following format.
+
+@verbatim
+type target_event event [event-name]
+type target_state state [state-name]
+type target_reset mode [reset-mode]
+@end verbatim
+
+@deffn {Command} tcl_notifications [on/off]
+Toggle output of target notifications to the current Tcl RPC server.
+Only available from the Tcl RPC server.
+Defaults to off.
+
+@end deffn
+
@node FAQ
@chapter FAQ
@cindex faq
@enumerate
-@anchor{FAQ RTCK}
+@anchor{faqrtck}
@item @b{RTCK, also known as: Adaptive Clocking - What is it?}
@cindex RTCK
@cindex adaptive clocking
In order for the two to work together they must be synchronised
well enough to work; JTAG can't go ten times faster than the CPU,
-for example. There are 2 basic options:
+for example. There are 2 basic options:
@enumerate
@item
Use a special "adaptive clocking" circuit to change the JTAG
power).
For example, Atmel AT91SAM chips start operation from reset with
-a 32kHz system clock. Boot firmware may activate the main oscillator
+a 32kHz system clock. Boot firmware may activate the main oscillator
and PLL before switching to a faster clock (perhaps that 500 MHz
ARM926 scenario).
If you're using JTAG to debug that startup sequence, you must slow
-the JTAG clock to sometimes 1 to 4kHz. After startup completes,
+the JTAG clock to sometimes 1 to 4kHz. After startup completes,
JTAG can use a faster clock.
Consider also debugging a 500MHz ARM926 hand held battery powered
device that enters a low power ``deep sleep'' mode, at 32kHz CPU
-clock, between keystrokes unless it has work to do. When would
+clock, between keystrokes unless it has work to do. When would
that 5 MHz JTAG clock be usable?
@b{Solution #1 - A special circuit}
@b{Xilinx rule of thumb} is 1/12 the clock speed.
Note: most full speed FT2232 based JTAG adapters are limited to a
-maximum of 6MHz. The ones using USB high speed chips (FT2232H)
+maximum of 6MHz. The ones using USB high speed chips (FT2232H)
often support faster clock rates (and adaptive clocking).
You can still debug the 'low power' situations - you just need to
operation in your idle loops even if you don't otherwise change the CPU
clock rate.
That operation gates the CPU clock, and thus the JTAG clock; which
-prevents JTAG access. One consequence is not being able to @command{halt}
+prevents JTAG access. One consequence is not being able to @command{halt}
cores which are executing that @emph{wait for interrupt} operation.
To set the JTAG frequency use the command:
@item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
are described, there is a parameter for specifying the clock frequency
-for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
+for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
specified in kilohertz. However, I do have a quartz crystal of a
frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
-i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
+i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
clock frequency?
No. The clock frequency specified here must be given as an integral number.
You can use the ``scan_chain'' command to verify and display the tap order.
Also, some commands can't execute until after @command{init} has been
-processed. Such commands include @command{nand probe} and everything
+processed. Such commands include @command{nand probe} and everything
else that needs to write to controller registers, perhaps for setting
up DRAM and loading it with code.
-@anchor{FAQ TAP Order}
+@anchor{faqtaporder}
@item @b{JTAG TAP Order} Do I have to declare the TAPS in some
particular order?
Many newer devices have multiple JTAG TAPs. For example: ST
Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
-``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
+``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
connected to the boundary scan TAP, which then connects to the
Cortex-M3 TAP, which then connects to the TDO pin.
@*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
'single-quote' operators in BASH shell scripts, with the added
-feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
+feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
nested 3 times@}@}@} NOTE: [date] is a bad example;
at this writing, Jim/OpenOCD does not have a date command.
@end itemize
@subsection The FOR command
-The most interesting command to look at is the FOR command. In Tcl,
+The most interesting command to look at is the FOR command. In Tcl,
the FOR command is normally implemented in C. Remember, FOR is a
command just like any other command.
// Execute the body
Execute_AsciiString( interp, argv[3] );
- // Execute the LOOP part
+ // Execute the LOOP part
Execute_AsciiString( interp, argv[4] );
@}
proc someproc @{@} @{
... multiple lines of stuff ...
@}
- $_TARGETNAME configure -event FOO someproc
+ $_TARGETNAME configure -event FOO someproc
#2 Good - no variables
$_TARGETNAME confgure -event foo "this ; that;"
#3 Good Curly Braces
@end enumerate
In the end, when the target event FOO occurs the TCLBODY is
-evaluated. Method @b{#1} and @b{#2} are functionally identical. For
+evaluated. Method @b{#1} and @b{#2} are functionally identical. For
Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
Remember the parsing rules. In case #3, @{curly-braces@} mean the
you must say so. See also ``upvar''. Example:
@example
proc myproc @{ @} @{
- set y 0 #Local variable Y
+ set y 0 #Local variable Y
global x #Global variable X
puts [format "X=%d, Y=%d" $x $y]
@}
@b{Dynamic variable creation}
@example
# Dynamically create a bunch of variables.
-for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
+for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
# Create var name
set vn [format "BIT%d" $x]
# Make it a global
global $vn
# Set it.
- set $vn [expr (1 << $x)]
+ set $vn [expr (1 << $x)]
@}
@end example
@b{Dynamic proc/command creation}
Code Review / openocd.git / blobdiff