@end deffn
@deffn {Interface Driver} {jlink}
-Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
+Segger J-Link family of USB adapters. It currently supports JTAG and SWD transports.
@quotation Compatibility Note
Segger released many firmware versions for the many harware versions they
only relevant on boards which have more than one target.
@end deffn
-@section Target CPU Types and Variants
+@section Target CPU Types
@cindex target type
@cindex CPU type
-@cindex CPU variant
Each target has a @dfn{CPU type}, as shown in the output of
the @command{targets} command. You need to specify that type
(@pxref{Architecture and Core Commands}),
and more.
-For some CPU types, OpenOCD also defines @dfn{variants} which
-indicate differences that affect their handling.
-For example, a particular implementation bug might need to be
-worked around in some chip versions.
-
It's easy to see what target types are supported,
since there's a command to list them.
-However, there is currently no way to list what target variants
-are supported (other than by reading the OpenOCD source code).
@anchor{targettypes}
@deffn Command {target types}
Lists all supported target types.
-At this writing, the supported CPU types and variants are:
+At this writing, the supported CPU types are:
@itemize @bullet
@item @code{arm11} -- this is a generation of ARMv6 cores
(Support for this is still incomplete.)
@item @code{fa526} -- resembles arm920 (w/o Thumb)
@item @code{feroceon} -- resembles arm926
-@item @code{mips_m4k} -- a MIPS core. This supports one variant:
+@item @code{mips_m4k} -- a MIPS core
@item @code{xscale} -- this is actually an architecture,
not a CPU type. It is based on the ARMv5 architecture.
-There are several variants defined:
-@itemize @minus
-@item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
-@code{pxa27x} ... instruction register length is 7 bits
-@item @code{pxa250}, @code{pxa255},
-@code{pxa26x} ... instruction register length is 5 bits
-@item @code{pxa3xx} ... instruction register length is 11 bits
-@end itemize
@item @code{openrisc} -- this is an OpenRISC 1000 core.
The current implementation supports three JTAG TAP cores:
@itemize @minus
@item @var{configparams} ... all parameters accepted by
@command{$target_name configure} are permitted.
If the target is big-endian, set it here with @code{-endian big}.
-If the variant matters, set it here with @code{-variant}.
You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
@end itemize
@emph{Warning:} changing some of these after setup is dangerous.
For example, moving a target from one TAP to another;
-and changing its endianness or variant.
+and changing its endianness.
@itemize @bullet
two different handlers, but calling it twice with the
same event name assigns only one handler.
-@item @code{-variant} @var{name} -- specifies a variant of the target,
-which OpenOCD needs to know about.
-
@item @code{-work-area-backup} (@option{0}|@option{1}) -- says
whether the work area gets backed up; by default,
@emph{it is not backed up.}
@end example
@end deffn
+@anchor{at91samd}
+@deffn {Flash Driver} at91samd
+@cindex at91samd
+
+@deffn Command {at91samd chip-erase}
+Issues a complete Flash erase via the Device Service Unit (DSU). This can be
+used to erase a chip back to its factory state and does not require the
+processor to be halted.
+@end deffn
+
+@deffn Command {at91samd set-security}
+Secures the Flash via the Set Security Bit (SSB) command. This prevents access
+to the Flash and can only be undone by using the chip-erase command which
+erases the Flash contents and turns off the security bit. Warning: at this
+time, openocd will not be able to communicate with a secured chip and it is
+therefore not possible to chip-erase it without using another tool.
+
+@example
+at91samd set-security enable
+@end example
+@end deffn
+
+@end deffn
+
@anchor{at91sam3}
@deffn {Flash Driver} at91sam3
@cindex at91sam3