Doc: jtag_init must validate scan chain too

[openocd.git] / doc / openocd.texi

diff --git a/doc/openocd.texi b/doc/openocd.texi
index fd4f9f7f68bdabd34d5821a33fa87ff126dbd8f8..7ebe45788a93c5dc87398583fb12e546dd208745 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1573,6 +1573,11 @@ which uses only a lightweight JTAG reset before examining the
 scan chain.
 If that fails, it tries again, using a harder reset
 from the overridable procedure @command{init_reset}.
+
+Implementations must have verified the JTAG scan chain before
+they return.
+This is done by calling @command{jtag arp_init}
+(or @command{jtag arp_init-reset}).
 @end deffn
 
 @anchor{TCP/IP Ports}
@@ -2221,6 +2226,12 @@ needing to cope with both architecture and board specific constraints.
 
 @section Commands for Handling Resets
 
+@deffn {Command} jtag_nsrst_assert_width milliseconds
+Minimum amount of time (in milliseconds) OpenOCD should wait
+after asserting nSRST (active-low system reset) before
+allowing it to be deasserted.
+@end deffn
+
 @deffn {Command} jtag_nsrst_delay milliseconds
 How long (in milliseconds) OpenOCD should wait after deasserting
 nSRST (active-low system reset) before starting new JTAG operations.
@@ -2228,6 +2239,12 @@ When a board has a reset button connected to SRST line it will
 probably have hardware debouncing, implying you should use this.
 @end deffn
 
+@deffn {Command} jtag_ntrst_assert_width milliseconds
+Minimum amount of time (in milliseconds) OpenOCD should wait
+after asserting nTRST (active-low JTAG TAP reset) before
+allowing it to be deasserted.
+@end deffn
+
 @deffn {Command} jtag_ntrst_delay milliseconds
 How long (in milliseconds) OpenOCD should wait after deasserting
 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
@@ -6075,6 +6092,15 @@ TAP @code{post-reset} events are delivered to all TAPs
 with handlers for that event.
 @end deffn
 
+@deffn Command {pathmove} start_state [next_state ...]
+Start by moving to @var{start_state}, which
+must be one of the @emph{stable} states.
+Then, in a series of single state transitions
+(conforming to the JTAG state machine) shift to
+each @var{next_state} in sequence, one per TCK cycle.
+The final state must also be stable.
+@end deffn
+
 @deffn Command {runtest} @var{num_cycles}
 Move to the @sc{run/idle} state, and execute at least
 @var{num_cycles} of the JTAG clock (TCK).
@@ -6102,23 +6128,30 @@ Default is enabled.
 @cindex TAP state names
 
 The @var{tap_state} names used by OpenOCD in the @command{drscan},
-and @command{irscan} commands are:
+@command{irscan}, and @command{pathmove} commands are the same
+as those used in SVF boundary scan documents, except that some
+versions of SVF use @sc{idle} instead of @sc{run/idle}.
 
 @itemize @bullet
-@item @b{RESET} ... acts as if TRST were pulsed
-@item @b{RUN/IDLE} ... don't assume this always means IDLE
+@item @b{RESET} ... @emph{stable} (with TMS high);
+acts as if TRST were pulsed
+@item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
 @item @b{DRSELECT}
 @item @b{DRCAPTURE}
-@item @b{DRSHIFT} ... TDI/TDO shifting through the data register
+@item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
+through the data register
 @item @b{DREXIT1}
-@item @b{DRPAUSE} ... data register ready for update or more shifting
+@item @b{DRPAUSE} ... @emph{stable}; data register ready
+for update or more shifting
 @item @b{DREXIT2}
 @item @b{DRUPDATE}
 @item @b{IRSELECT}
 @item @b{IRCAPTURE}
-@item @b{IRSHIFT} ... TDI/TDO shifting through the instruction register
+@item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
+through the instruction register
 @item @b{IREXIT1}
-@item @b{IRPAUSE} ... instruction register ready for update or more shifting
+@item @b{IRPAUSE} ... @emph{stable}; instruction register ready
+for update or more shifting
 @item @b{IREXIT2}
 @item @b{IRUPDATE}
 @end itemize