+
+/*
+* On AT91SAM7S: When the gpnvm bits are set with
+* > at91sam7 gpnvm bitnr set
+* the changes are not visible in the flash controller status register MC_FSR
+* until the processor has been reset.
+* On the Olimex board this requires a power cycle.
+* Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
+* The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
+* Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
+*/
+COMMAND_HANDLER(at91sam7_handle_gpnvm_command)
+{
+ flash_bank_t *bank;
+ int bit;
+ uint8_t flashcmd;
+ uint32_t status;
+ at91sam7_flash_bank_t *at91sam7_info;
+ int retval;
+
+ if (argc != 2)
+ {
+ command_print(cmd_ctx, "at91sam7 gpnvm <bit> <set | clear>");
+ return ERROR_OK;
+ }
+
+ bank = get_flash_bank_by_num_noprobe(0);
+ if (bank == NULL)
+ {
+ return ERROR_FLASH_BANK_INVALID;
+ }
+ if (strcmp(bank->driver->name, "at91sam7"))
+ {
+ command_print(cmd_ctx, "not an at91sam7 flash bank '%s'", args[0]);
+ return ERROR_FLASH_BANK_INVALID;
+ }
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("target has to be halted to perform flash operation");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (strcmp(args[1], "set") == 0)
+ {
+ flashcmd = SGPB;
+ }
+ else if (strcmp(args[1], "clear") == 0)
+ {
+ flashcmd = CGPB;
+ }
+ else
+ {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ at91sam7_info = bank->driver_priv;
+ if (at91sam7_info->cidr == 0)
+ {
+ retval = at91sam7_read_part_info(bank);
+ if (retval != ERROR_OK)
+ {
+ return retval;
+ }
+ }
+
+ COMMAND_PARSE_NUMBER(int, args[0], bit);
+ if ((bit < 0) || (bit >= at91sam7_info->num_nvmbits))
+ {
+ command_print(cmd_ctx, "gpnvm bit '#%s' is out of bounds for target %s", args[0], at91sam7_info->target_name);
+ return ERROR_OK;
+ }
+
+ /* Configure the flash controller timing */
+ at91sam7_read_clock_info(bank);
+ at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
+
+ if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
+ {
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
+ status = at91sam7_get_flash_status(bank->target, 0);
+ LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32 " \n", flashcmd, bit, status);
+
+ /* check protect state */
+ at91sam7_protect_check(bank);
+
+ return ERROR_OK;
+}
+
+static int at91sam7_register_commands(struct command_context_s *cmd_ctx)
+{
+ command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7",
+ NULL, COMMAND_ANY, NULL);
+
+ register_command(cmd_ctx, at91sam7_cmd, "gpnvm",
+ at91sam7_handle_gpnvm_command, COMMAND_EXEC,
+ "at91sam7 gpnvm <bit> set | clear, "
+ "set or clear one gpnvm bit");
+
+ return ERROR_OK;
+}
+
+flash_driver_t at91sam7_flash = {
+ .name = "at91sam7",
+ .register_commands = &at91sam7_register_commands,
+ .flash_bank_command = &at91sam7_flash_bank_command,
+ .erase = &at91sam7_erase,
+ .protect = &at91sam7_protect,
+ .write = &at91sam7_write,
+ .probe = &at91sam7_probe,
+ .auto_probe = &at91sam7_probe,
+ .erase_check = &at91sam7_erase_check,
+ .protect_check = &at91sam7_protect_check,
+ .info = &at91sam7_info,
+ };