u32 cidr, status;
int sectornum;
- if (bank->target->state != TARGET_HALTED)
- {
- return ERROR_TARGET_NOT_HALTED;
- }
-
/* Read and parse chip identification register */
target_read_u32(target, DBGU_CIDR, &cidr);
if (at91sam7_info->cidr_arch == 0x72 )
{
- at91sam7_info->num_nvmbits = 2;
- at91sam7_info->nvmbits = (status>>8)&0x03;
+ at91sam7_info->num_nvmbits = 3;
+ at91sam7_info->nvmbits = (status>>8)&0x07;
bank->base = 0x100000;
bank->bus_width = 4;
if (bank->size==0x80000) /* AT91SAM7SE512 */
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+ if (bank->target->state != TARGET_HALTED)
+ {
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
if (at91sam7_info->cidr == 0)
{
at91sam7_read_part_info(bank);
{
return ERROR_TARGET_NOT_HALTED;
}
-
+
if (at91sam7_info->cidr == 0)
{
at91sam7_read_part_info(bank);
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
at91sam7_info->probed = 0;
+ if (bank->target->state != TARGET_HALTED)
+ {
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
if (at91sam7_info->cidr == 0)
{
at91sam7_read_part_info(bank);
int printed, flashplane;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+ if (bank->target->state != TARGET_HALTED)
+ {
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
at91sam7_read_part_info(bank);
if (at91sam7_info->cidr == 0)
}
/*
-* On AT91SAM7S: When the gpnmv bits are set with
+* On AT91SAM7S: When the gpnvm bits are set with
* > at91sam7 gpnvm 0 bitnr set
* the changes are not visible in the flash controller status register MC_FSR
* until the processor has been reset.
}
else
{
- command_print(cmd_ctx, "usage: at91sam7 gpnvm <num> <bit> <set|clear>");
- return ERROR_OK;
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
/* Configure the flash controller timing */