/* Read clock configuration and set at91sam7_info->mck_freq */
static void at91sam7_read_clock_info(flash_bank_t *bank)
{
- at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+ struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
uint32_t mckr, mcfr, pllr, mor;
unsigned long tmp = 0, mainfreq;
static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode)
{
uint32_t fmr, fmcn = 0, fws = 0;
- at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+ struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
if (mode && (mode != at91sam7_info->flashmode))
static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen)
{
uint32_t fcr;
- at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+ struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
static int at91sam7_read_part_info(struct flash_bank_s *bank)
{
flash_bank_t *t_bank = bank;
- at91sam7_flash_bank_t *at91sam7_info;
+ struct at91sam7_flash_bank *at91sam7_info;
target_t *target = t_bank->target;
uint16_t bnk, sec;
flash_bank_t *fb = malloc(sizeof(flash_bank_t));
fb->target = target;
fb->driver = bank->driver;
- fb->driver_priv = malloc(sizeof(at91sam7_flash_bank_t));
+ fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank));
fb->next = NULL;
/* link created bank in 'flash_banks' list and redirect t_bank */
t_bank->num_sectors = sectors_num;
/* allocate sectors */
- t_bank->sectors = malloc(sectors_num * sizeof(flash_sector_t));
+ t_bank->sectors = malloc(sectors_num * sizeof(struct flash_sector));
for (sec = 0; sec < sectors_num; sec++)
{
t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
uint8_t lock_pos, gpnvm_pos;
uint32_t status;
- at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+ struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
if (at91sam7_info->cidr == 0)
{
return ERROR_OK;
}
-static int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
+FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
{
flash_bank_t *t_bank = bank;
- at91sam7_flash_bank_t *at91sam7_info;
+ struct at91sam7_flash_bank *at91sam7_info;
target_t *target = t_bank->target;
uint32_t base_address;
int bnk, sec;
- at91sam7_info = malloc(sizeof(at91sam7_flash_bank_t));
+ at91sam7_info = malloc(sizeof(struct at91sam7_flash_bank));
t_bank->driver_priv = at91sam7_info;
/* part wasn't probed for info yet */
flash_bank_t *fb = malloc(sizeof(flash_bank_t));
fb->target = target;
fb->driver = bank->driver;
- fb->driver_priv = malloc(sizeof(at91sam7_flash_bank_t));
+ fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank));
fb->next = NULL;
/* link created bank in 'flash_banks' list and redirect t_bank */
t_bank->num_sectors = num_sectors;
/* allocate sectors */
- t_bank->sectors = malloc(num_sectors * sizeof(flash_sector_t));
+ t_bank->sectors = malloc(num_sectors * sizeof(struct flash_sector));
for (sec = 0; sec < num_sectors; sec++)
{
t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
static int at91sam7_erase(struct flash_bank_s *bank, int first, int last)
{
- at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+ struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
int sec;
uint32_t nbytes, pos;
uint8_t *buffer;
int sector;
uint32_t pagen;
- at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+ struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
if (at91sam7_info->cidr == 0)
{
static int at91sam7_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
int retval;
- at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+ struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
uint32_t dst_min_alignment, wcount, bytes_remaining = count;
uint32_t first_page, last_page, pagen, buffer_pos;
static int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
int printed;
- at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
+ struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
if (at91sam7_info->cidr == 0)
{
* The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
* Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
*/
-static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(at91sam7_handle_gpnvm_command)
{
flash_bank_t *bank;
int bit;
uint8_t flashcmd;
uint32_t status;
- at91sam7_flash_bank_t *at91sam7_info;
+ struct at91sam7_flash_bank *at91sam7_info;
int retval;
if (argc != 2)
return ERROR_OK;
}
-flash_driver_t at91sam7_flash = {
+struct flash_driver at91sam7_flash = {
.name = "at91sam7",
.register_commands = &at91sam7_register_commands,
.flash_bank_command = &at91sam7_flash_bank_command,