* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
* read/write data to the SLC controller.
* - DMA descriptors will be put at start of working area,
* - Hardware generated ECC will be stored at ECC_OFFS
- * - OOB wil be read/written from/to SPARE_OFFS
+ * - OOB will be read/written from/to SPARE_OFFS
* - Actual page data will be read from/to DATA_OFFS
* There are unused holes between the used areas.
*/
#define SPARE_OFFS 0x140
#define DATA_OFFS 0x200
-static int sp_ooblayout[] = {
+static const int sp_ooblayout[] = {
10, 11, 12, 13, 14, 15
};
-static int lp_ooblayout[] = {
+static const int lp_ooblayout[] = {
40, 41, 42, 43, 44, 45,
46, 47, 48, 49, 50, 51,
52, 53, 54, 55, 56, 57,
}
/* after reset set other registers of SLC,
- * so reset calling is here at the begining
+ * so reset calling is here at the beginning
*/
retval = lpc32xx_reset(nand);
if (ERROR_OK != retval)
WIDTH = bus_width)
*/
retval = target_write_u32(target, 0x20020014,
- 0x3e | (bus_width == 16) ? 1 : 0);
+ 0x3e | ((bus_width == 16) ? 1 : 0));
if (ERROR_OK != retval) {
LOG_ERROR("could not set SLC_CFG");
return ERROR_NAND_OPERATION_FAILED;
* 2. Copy generated ECC data from Register to Spare Area
* 3. X'fer next 256 bytes of data from Memory to Flash.
* 4. Copy generated ECC data from Register to Spare Area.
- * 5. X'fer 16 byets of Spare area from Memory to Flash.
+ * 5. X'fer 16 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Small Block NAND
* ----------------------------------------------------------
* 1. X'fer 256 bytes of data from Flash to Memory.
* 5. X'fer 16 bytes of Spare area from Flash to Memory.
* Write Operation Sequence for Large Block NAND
* ----------------------------------------------------------
- * 1. Steps(1-4) of Write Operations repeate for four times
+ * 1. Steps(1-4) of Write Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Large Block NAND
* ----------------------------------------------------------
- * 1. Steps(1-4) of Read Operations repeate for four times
+ * 1. Steps(1-4) of Read Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Flash to Memory.
* 2. Copy generated ECC data from Register to Spare Area
* 3. X'fer next 256 bytes of data from Memory to Flash.
* 4. Copy generated ECC data from Register to Spare Area.
- * 5. X'fer 16 byets of Spare area from Memory to Flash.
+ * 5. X'fer 16 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Small Block NAND
* ----------------------------------------------------------
* 1. X'fer 256 bytes of data from Flash to Memory.
* 5. X'fer 16 bytes of Spare area from Flash to Memory.
* Write Operation Sequence for Large Block NAND
* ----------------------------------------------------------
- * 1. Steps(1-4) of Write Operations repeate for four times
+ * 1. Steps(1-4) of Write Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Large Block NAND
* ----------------------------------------------------------
- * 1. Steps(1-4) of Read Operations repeate for four times
+ * 1. Steps(1-4) of Read Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Flash to Memory.
int retval;
uint32_t target_mem_base;
- LOG_DEBUG("SLC write page %x data=%d, oob=%d, "
- "data_size=%d, oob_size=%d",
+ LOG_DEBUG("SLC write page %" PRIx32 " data=%d, oob=%d, "
+ "data_size=%" PRIu32 ", oob_size=%" PRIu32,
page, data != 0, oob != 0, data_size, oob_size);
target_mem_base = pworking_area->address;
/*
- * Skip writting page which has all 0xFF data as this will
+ * Skip writing page which has all 0xFF data as this will
* generate 0x0 value.
*/
if (data && !oob) {
return retval;
}
- /* Write first decriptor to DMA controller */
+ /* Write first descriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
sizeof(dmac_ll_t) / 4,
(uint8_t *)dmalist);
/* Copy to oob, at correct offsets */
static uint8_t ecc[24];
slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
- int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
+ const int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
int i;
for (i = 0; i < ecc_count * 3; i++)
foob[layout[i]] = ecc[i];
return retval;
}
- /* Write OOB decriptor to DMA controller */
+ /* Write OOB descriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
sizeof(dmac_ll_t) / 4,
(uint8_t *)(&dmalist[nll-1]));
int retval;
uint32_t target_mem_base;
- LOG_DEBUG("SLC read page %x data=%d, oob=%d",
+ LOG_DEBUG("SLC read page %" PRIx32 " data=%" PRIu32 ", oob=%" PRIu32,
page, data_size, oob_size);
target_mem_base = pworking_area->address;
return retval;
}
- /* Write first decriptor to DMA controller */
+ /* Write first descriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist);
if (ERROR_OK != retval) {
slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
/* Copy ECC from flash using correct layout */
static uint8_t fecc[24];/* max size */
- int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
+ const int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
int i;
for (i = 0; i < ecc_count * 3; i++)
fecc[i] = foob[layout[i]];
retval = nand_correct_data(nand, data + 256*i, &fecc[i * 3],
&ecc[i * 3]);
if (retval > 0)
- LOG_WARNING("error detected and corrected: %d/%d",
+ LOG_WARNING("error detected and corrected: %" PRIu32 "/%d",
page, i);
if (retval < 0)
break;
if (i == ecc_count)
retval = ERROR_OK;
else {
- LOG_ERROR("uncorrectable error detected: %d/%d", page, i);
+ LOG_ERROR("uncorrectable error detected: %" PRIu32 "/%d", page, i);
retval = ERROR_NAND_OPERATION_FAILED;
}
return retval;
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
struct nand_device *nand = get_nand_device_by_num(num);
if (!nand) {
- command_print(CMD_CTX, "nand device '#%s' is out of bounds",
+ command_print(CMD, "nand device '#%s' is out of bounds",
CMD_ARGV[0]);
return ERROR_OK;
}
return ERROR_COMMAND_SYNTAX_ERROR;
}
- command_print(CMD_CTX, "%s controller selected",
+ command_print(CMD, "%s controller selected",
selected[lpc32xx_info->selected_controller]);
return ERROR_OK;
Code Review / openocd.git / blobdiff