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flash/nor/at91sam3: remove sam3_page_write_opcodes
[openocd.git] / src / flash / nor / at91sam3.c
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index bbdb58cb2482b4ad3d0bea553b9af41b93b2cb10..9d119bbf588b65052c1da3ff23ae66ee8b82152f 100644 (file)
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -1518,6 +1518,143 @@ static const struct sam3_chip_details all_sam3_details[] = {
                },
        },
 
+       {
+               .chipid_cidr    = 0x29480360,
+               .name           = "at91sam3n0b",
+               .total_flash_size     = 32 * 1024,
+               .total_sram_size      = 8 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 1,
+
+/*             .bank[0] = { */
+               {
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_N,
+                               .controller_address = 0x400e0A00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 32 * 1024,
+                               .nsectors   = 2,
+                               .sector_size = 16384,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
+               },
+       },
+
+       {
+               .chipid_cidr    = 0x29380360,
+               .name           = "at91sam3n0a",
+               .total_flash_size     = 32 * 1024,
+               .total_sram_size      = 8 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 1,
+
+/*             .bank[0] = { */
+               {
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_N,
+                               .controller_address = 0x400e0A00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 32 * 1024,
+                               .nsectors   = 2,
+                               .sector_size = 16384,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
+               },
+       },
+
+       {
+               .chipid_cidr    = 0x29450260,
+               .name           = "at91sam3n00b",
+               .total_flash_size     = 16 * 1024,
+               .total_sram_size      = 4 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 1,
+
+/*             .bank[0] = { */
+               {
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_N,
+                               .controller_address = 0x400e0A00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 16 * 1024,
+                               .nsectors   = 1,
+                               .sector_size = 16384,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
+               },
+       },
+
+       {
+               .chipid_cidr    = 0x29350260,
+               .name           = "at91sam3n00a",
+               .total_flash_size     = 16 * 1024,
+               .total_sram_size      = 4 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 1,
+
+/*             .bank[0] = { */
+               {
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_N,
+                               .controller_address = 0x400e0A00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 16 * 1024,
+                               .nsectors   = 1,
+                               .sector_size = 16384,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
+               },
+       },
+
+
        /* Start at91sam3a series*/
        /* System boots at address 0x0 */
        /* gpnvm[1] = selects boot code */
@@ -2993,7 +3130,7 @@ static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
        pDetails = all_sam3_details;
        while (pDetails->name) {
                /* Compare cidr without version bits */
-               if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
+               if (((pDetails->chipid_cidr ^ pPrivate->pChip->cfg.CHIPID_CIDR) & 0xFFFFFFE0) == 0)
                        break;
                else
                        pDetails++;
@@ -3198,93 +3335,6 @@ static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum,
        return r;
 }
 
-/* The code below is basically this: */
-/* compiled with */
-/* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
-/*  */
-/* Only the *CPU* can write to the flash buffer. */
-/* the DAP cannot... so - we download this 28byte thing */
-/* Run the algorithm - (below) */
-/* to program the device */
-/*  */
-/* ======================================== */
-/* #include <stdint.h> */
-/*  */
-/* struct foo { */
-/*   uint32_t *dst; */
-/*   const uint32_t *src; */
-/*   int   n; */
-/*   volatile uint32_t *base; */
-/*   uint32_t   cmd; */
-/* }; */
-/*  */
-/*  */
-/* uint32_t sam3_function(struct foo *p) */
-/* { */
-/*   volatile uint32_t *v; */
-/*   uint32_t *d; */
-/*   const uint32_t *s; */
-/*   int   n; */
-/*   uint32_t r; */
-/*  */
-/*   d = p->dst; */
-/*   s = p->src; */
-/*   n = p->n; */
-/*  */
-/*   do { */
-/*     *d++ = *s++; */
-/*   } while (--n) */
-/*     ; */
-/*  */
-/*   v = p->base; */
-/*  */
-/*   v[ 1 ] = p->cmd; */
-/*   do { */
-/*     r = v[8/4]; */
-/*   } while (!(r&1)) */
-/*     ; */
-/*   return r; */
-/* } */
-/* ======================================== */
-
-static const uint8_t
-       sam3_page_write_opcodes[] = {
-       /*  24 0000 0446                mov     r4, r0 */
-       0x04, 0x46,
-       /*  25 0002 6168                ldr     r1, [r4, #4] */
-       0x61, 0x68,
-       /*  26 0004 0068                ldr     r0, [r0, #0] */
-       0x00, 0x68,
-       /*  27 0006 A268                ldr     r2, [r4, #8] */
-       0xa2, 0x68,
-       /*  28                          @ lr needed for prologue */
-       /*  29                  .L2: */
-       /*  30 0008 51F8043B            ldr     r3, [r1], #4 */
-       0x51, 0xf8, 0x04, 0x3b,
-       /*  31 000c 12F1FF32            adds    r2, r2, #-1 */
-       0x12, 0xf1, 0xff, 0x32,
-       /*  32 0010 40F8043B            str     r3, [r0], #4 */
-       0x40, 0xf8, 0x04, 0x3b,
-       /*  33 0014 F8D1                bne     .L2 */
-       0xf8, 0xd1,
-       /*  34 0016 E268                ldr     r2, [r4, #12] */
-       0xe2, 0x68,
-       /*  35 0018 2369                ldr     r3, [r4, #16] */
-       0x23, 0x69,
-       /*  36 001a 5360                str     r3, [r2, #4] */
-       0x53, 0x60,
-       /*  37 001c 0832                adds    r2, r2, #8 */
-       0x08, 0x32,
-       /*  38                  .L4: */
-       /*  39 001e 1068                ldr     r0, [r2, #0] */
-       0x10, 0x68,
-       /*  40 0020 10F0010F            tst     r0, #1 */
-       0x10, 0xf0, 0x01, 0x0f,
-       /*  41 0024 FBD0                beq     .L4 */
-       0xfb, 0xd0,
-       0x00, 0xBE                              /* bkpt #0 */
-};
-
 static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
 {
        uint32_t adr;
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