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Fix spelling of ARM Cortex
[openocd.git] / src / flash / nor / at91sam4.c
diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index 6e53b4e94da78987d9db66fdbdc0d7f3731cad6c..bcaaaa0fd1bff2739393028c52980d74f5317262 100644 (file)
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -296,6 +296,173 @@ static const struct sam4_chip_details all_sam4_details[] = {
                },
        },
 
+       /* Start at91sam4n* series */
+       /*atsam4n8a - LQFP48/QFN48*/
+       {
+               .chipid_cidr    = 0x293B0AE0,
+               .name           = "at91sam4n8a",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  512 * 1024,
+                       .nsectors   =  64,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+       /*atsam4n8b - LQFP64/QFN64*/
+       {
+               .chipid_cidr    = 0x294B0AE0,
+               .name           = "at91sam4n8b",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  512 * 1024,
+                       .nsectors   =  64,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+       /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
+       {
+               .chipid_cidr    = 0x295B0AE0,
+               .name           = "at91sam4n8c",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  512 * 1024,
+                       .nsectors   =  64,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+       /*atsam4n16b - LQFP64/QFN64*/
+       {
+               .chipid_cidr    = 0x29460CE0,
+               .name           = "at91sam4n16b",
+               .total_flash_size     = 1024 * 1024,
+               .total_sram_size      = 80 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  1024 * 1024,
+                       .nsectors   =  128,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+       /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
+       {
+               .chipid_cidr    = 0x29560CE0,
+               .name           = "at91sam4n16c",
+               .total_flash_size     = 1024 * 1024,
+               .total_sram_size      = 80 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  1024 * 1024,
+                       .nsectors   =  128,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+
        /* Start at91sam4s* series */
        /*atsam4s16c - LQFP100/BGA100*/
        {
@@ -363,6 +530,39 @@ static const struct sam4_chip_details all_sam4_details[] = {
                  },
                },
        },
+       /*atsam4sa16b - LQFP64/QFN64*/
+       {
+               .chipid_cidr    = 0x28970CE0,
+               .name           = "at91sam4sa16b",
+               .total_flash_size     = 1024 * 1024,
+               .total_sram_size      = 160 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  1024 * 1024,
+                       .nsectors   =  128,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
        /*atsam4s16a - LQFP48/QFN48*/
        {
                .chipid_cidr    = 0x288C0CE0,
@@ -574,6 +774,94 @@ static const struct sam4_chip_details all_sam4_details[] = {
                },
        },
 
+       /*at91sam4sd16c*/
+       {
+               .chipid_cidr    = 0x29a70ce0,
+               .name           = "at91sam4sd16c",
+               .total_flash_size     = 1024 * 1024,
+               .total_sram_size      = 160 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 2,
+
+/*             .bank[0] = { */
+               {
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  512 * 1024,
+                               .nsectors   =  64,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 1,
+                               .base_address = FLASH_BANK1_BASE_1024K_SD,
+                               .controller_address = 0x400e0c00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  512 * 1024,
+                               .nsectors   =  64,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+               },
+       },
+
+       /*at91sam4sa16c*/
+       {
+               .chipid_cidr    = 0x28a70ce0,
+               .name           = "at91sam4sa16c",
+               .total_flash_size     = 1024 * 1024,
+               .total_sram_size      = 160 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 2,
+
+/*             .bank[0] = { */
+               {
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  512 * 1024,
+                               .nsectors   =  64,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 1,
+                               .base_address = FLASH_BANK1_BASE_1024K_SD,
+                               .controller_address = 0x400e0c00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  512 * 1024,
+                               .nsectors   =  64,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+               },
+       },
+
        /* at91samg53n19 */
        {
                .chipid_cidr    = 0x247e0ae0,
@@ -1119,11 +1407,11 @@ static const char *const eproc_names[] = {
        _unknown,                                       /* 0 */
        "arm946es",                                     /* 1 */
        "arm7tdmi",                                     /* 2 */
-       "cortex-m3",                            /* 3 */
+       "Cortex-M3",                            /* 3 */
        "arm920t",                                      /* 4 */
        "arm926ejs",                            /* 5 */
-       "cortex-a5",                            /* 6 */
-       "cortex-m4",                            /* 7 */
+       "Cortex-A5",                            /* 6 */
+       "Cortex-M4",                            /* 7 */
        _unknown,                                       /* 8 */
        _unknown,                                       /* 9 */
        _unknown,                                       /* 10 */
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