}
}
-static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
+static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t address, uint32_t count)
{
struct target *target = bank->target;
arm_algo.core_state = ARM_STATE_ARM;
} else {
LOG_ERROR("Unknown architecture");
- return ERROR_FAIL;
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
cfi_intel_clear_status_register(bank);
return retval;
}
-static int cfi_spansion_write_block_mips(struct flash_bank *bank, uint8_t *buffer,
+static int cfi_spansion_write_block_mips(struct flash_bank *bank, const uint8_t *buffer,
uint32_t address, uint32_t count)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
}
;
- init_reg_param(®_params[0], "a0", 32, PARAM_OUT);
- init_reg_param(®_params[1], "a1", 32, PARAM_OUT);
- init_reg_param(®_params[2], "a2", 32, PARAM_OUT);
- init_reg_param(®_params[3], "a3", 32, PARAM_OUT);
- init_reg_param(®_params[4], "t0", 32, PARAM_OUT);
- init_reg_param(®_params[5], "t1", 32, PARAM_IN);
- init_reg_param(®_params[6], "t4", 32, PARAM_OUT);
- init_reg_param(®_params[7], "t5", 32, PARAM_OUT);
- init_reg_param(®_params[8], "t6", 32, PARAM_OUT);
- init_reg_param(®_params[9], "t7", 32, PARAM_OUT);
+ init_reg_param(®_params[0], "r4", 32, PARAM_OUT);
+ init_reg_param(®_params[1], "r5", 32, PARAM_OUT);
+ init_reg_param(®_params[2], "r6", 32, PARAM_OUT);
+ init_reg_param(®_params[3], "r7", 32, PARAM_OUT);
+ init_reg_param(®_params[4], "r8", 32, PARAM_OUT);
+ init_reg_param(®_params[5], "r9", 32, PARAM_IN);
+ init_reg_param(®_params[6], "r12", 32, PARAM_OUT);
+ init_reg_param(®_params[7], "r13", 32, PARAM_OUT);
+ init_reg_param(®_params[8], "r14", 32, PARAM_OUT);
+ init_reg_param(®_params[9], "r15", 32, PARAM_OUT);
while (count > 0) {
uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
return retval;
}
-static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
+static int cfi_spansion_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t address, uint32_t count)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
arm_algo = &armv4_5_algo;
} else {
LOG_ERROR("Unknown architecture");
- return ERROR_FAIL;
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
int target_code_size = 0;
return ERROR_OK;
}
-static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word,
+static int cfi_intel_write_words(struct flash_bank *bank, const uint8_t *word,
uint32_t wordcount, uint32_t address)
{
int retval;
return ERROR_OK;
}
-static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word,
+static int cfi_spansion_write_words(struct flash_bank *bank, const uint8_t *word,
uint32_t wordcount, uint32_t address)
{
int retval;
return ERROR_FLASH_OPERATION_FAILED;
}
-static int cfi_write_words(struct flash_bank *bank, uint8_t *word,
+static int cfi_write_words(struct flash_bank *bank, const uint8_t *word,
uint32_t wordcount, uint32_t address)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
return ERROR_OK;
}
-static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct target *target = bank->target;