* - 822 | 4 (tested with LPC824)
* - 8N04
* - NHS31xx (tested with NHS3100)
+ * - 844 | 5 (tested with LPC845)
*
* lpc1100:
* - 11xx
#define NHS3152 0x4e315220
#define NHS3153 0x4e315320 /* Only specified in Rev.1 of the datasheet */
+#define LPC844_201 0x00008441
+#define LPC844_201_1 0x00008442
+#define LPC844_201_2 0x00008444
+
+#define LPC845_301 0x00008451
+#define LPC845_301_1 0x00008452
+#define LPC845_301_2 0x00008453
+#define LPC845_301_3 0x00008454
+
#define IAP_CODE_LEN 0x34
#define LPC11xx_REG_SECTORS 24
int checksum_vector;
uint32_t iap_max_stack;
uint32_t lpc4300_bank;
+ uint32_t iap_entry_alternative;
bool probed;
};
lpc2000_info->cmd51_max_buffer = 1024; /* For LPC824, has 8kB of SRAM */
bank->num_sectors = 32;
break;
+ case 64 * 1024:
+ lpc2000_info->cmd51_max_buffer = 1024; /* For LPC844, has 8kB of SRAM */
+ bank->num_sectors = 64;
+ break;
default:
LOG_ERROR("BUG: unknown bank->size encountered");
exit(-1);
int retval = target_write_memory(target, (*iap_working_area)->address, 4, 2, jump_gate);
if (retval != ERROR_OK) {
- LOG_ERROR("Write memory at address 0x%8.8" TARGET_PRIxADDR " failed (check work_area definition)",
+ LOG_ERROR("Write memory at address " TARGET_ADDR_FMT " failed (check work_area definition)",
(*iap_working_area)->address);
target_free_working_area(target, *iap_working_area);
}
exit(-1);
}
+ if (lpc2000_info->iap_entry_alternative != 0x0)
+ iap_entry_point = lpc2000_info->iap_entry_alternative;
+
struct mem_param mem_params[2];
/* command parameter table */
if (strcmp(CMD_ARGV[8], "calc_checksum") == 0)
lpc2000_info->calc_checksum = 1;
}
+ if (CMD_ARGC >= 10 && !lpc2000_info->iap_entry_alternative)
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[9], lpc2000_info->iap_entry_alternative);
return ERROR_OK;
}
free(last_buffer);
}
- LOG_DEBUG("writing 0x%" PRIx32 " bytes to address 0x%" PRIx32, thisrun_bytes,
- bank->base + offset + bytes_written);
+ LOG_DEBUG("writing 0x%" PRIx32 " bytes to address " TARGET_ADDR_FMT,
+ thisrun_bytes, bank->base + offset + bytes_written);
/* Write data */
param_table[0] = bank->base + offset + bytes_written;
bank->size = 30 * 1024;
break;
+ case LPC844_201:
+ case LPC844_201_1:
+ case LPC844_201_2:
+ case LPC845_301:
+ case LPC845_301_1:
+ case LPC845_301_2:
+ case LPC845_301_3:
+ lpc2000_info->variant = lpc800;
+ bank->size = 64 * 1024;
+ break;
+
default:
LOG_ERROR("BUG: unknown Part ID encountered: 0x%" PRIx32, part_id);
exit(-1);
COMMAND_REGISTRATION_DONE
};
-struct flash_driver lpc2000_flash = {
+const struct flash_driver lpc2000_flash = {
.name = "lpc2000",
.commands = lpc2000_command_handlers,
.flash_bank_command = lpc2000_flash_bank_command,