nrf5: update links to compatibility matrixes for nrf5x variants

[openocd.git] / src / flash / nor / nrf5.c

diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index ad80e02e0d1e20dced366a88696d336ea8cd6f0f..5266f3dab81a22a74d36d5c898ab0377f02fdcf8 100644 (file)
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -26,6 +26,7 @@
 #include <target/algorithm.h>
 #include <target/armv7m.h>
 #include <helper/types.h>
+#include <helper/time_support.h>
 
 enum {
        NRF5_FLASH_BASE = 0x00000000,
@@ -108,8 +109,10 @@ enum nrf5_nvmc_config_bits {
 
 struct nrf5_info {
        uint32_t code_page_size;
+       uint32_t refcount;
 
-       struct {
+       struct nrf5_bank {
+               struct nrf5_info *chip;
                bool probed;
                int (*write) (struct flash_bank *bank,
                              struct nrf5_info *chip,
@@ -135,11 +138,16 @@ struct nrf5_device_spec {
 .flash_size_kb = (fsize),                           \
 }
 
-/* The known devices table below is derived from the "nRF51 Series
- * Compatibility Matrix" document, which can be found by searching for
- * ATTN-51 on the Nordic Semi website:
+/* The known devices table below is derived from the "nRF5x series
+ * compatibility matrix" documents, which can be found in the "DocLib" of
+ * nordic:
  *
- * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
+ * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51422_ic_revision_overview
+ * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51822_ic_revision_overview
+ * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51824_ic_revision_overview
+ * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52810/latest/COMP/nrf52810/nRF52810_ic_revision_overview
+ * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52832/latest/COMP/nrf52832/ic_revision_overview
+ * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52840/latest/COMP/nrf52840/nRF52840_ic_revision_overview
  *
  * Up to date with Matrix v2.0, plus some additional HWIDs.
  *
@@ -202,18 +210,26 @@ static const struct nrf5_device_spec nrf5_known_devices_table[] = {
        NRF5_DEVICE_DEF(0x007A, "51422", "CEAA", "C0",    256),
        NRF5_DEVICE_DEF(0x0088, "51422", "CFAC", "A0",    256),
 
+       /* nRF52810 Devices */
+       NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0",    192),
+       NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0",    192),
+
        /* nRF52832 Devices */
        NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0",    512),
        NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0",    512),
+       NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0",    512),
+
+       /* nRF52840 Devices */
+       NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0",    1024),
 };
 
 static int nrf5_bank_is_probed(struct flash_bank *bank)
 {
-       struct nrf5_info *chip = bank->driver_priv;
+       struct nrf5_bank *nbank = bank->driver_priv;
 
-       assert(chip != NULL);
+       assert(nbank != NULL);
 
-       return chip->bank[bank->bank_number].probed;
+       return nbank->probed;
 }
 static int nrf5_probe(struct flash_bank *bank);
 
@@ -224,7 +240,8 @@ static int nrf5_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf5_i
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       *chip = bank->driver_priv;
+       struct nrf5_bank *nbank = bank->driver_priv;
+       *chip = nbank->chip;
 
        int probed = nrf5_bank_is_probed(bank);
        if (probed < 0)
@@ -239,7 +256,8 @@ static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
 {
        uint32_t ready;
        int res;
-       int timeout = 100;
+       int timeout_ms = 340;
+       int64_t ts_start = timeval_ms();
 
        do {
                res = target_read_u32(chip->target, NRF5_NVMC_READY, &ready);
@@ -251,8 +269,9 @@ static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
                if (ready == 0x00000001)
                        return ERROR_OK;
 
-               alive_sleep(1);
-       } while (timeout--);
+               keep_alive();
+
+       } while ((timeval_ms()-ts_start) < timeout_ms);
 
        LOG_DEBUG("Timed out waiting for NVMC_READY");
        return ERROR_FLASH_BUSY;
@@ -364,7 +383,8 @@ static int nrf5_protect_check(struct flash_bank *bank)
        if (bank->base == NRF5_UICR_BASE)
                return ERROR_OK;
 
-       struct nrf5_info *chip = bank->driver_priv;
+       struct nrf5_bank *nbank = bank->driver_priv;
+       struct nrf5_info *chip = nbank->chip;
 
        assert(chip != NULL);
 
@@ -450,7 +470,8 @@ static int nrf5_probe(struct flash_bank *bank)
 {
        uint32_t hwid;
        int res;
-       struct nrf5_info *chip = bank->driver_priv;
+       struct nrf5_bank *nbank = bank->driver_priv;
+       struct nrf5_info *chip = nbank->chip;
 
        res = target_read_u32(chip->target, NRF5_FICR_CONFIGID, &hwid);
        if (res != ERROR_OK) {
@@ -728,7 +749,8 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t offset, const ui
 static int nrf5_write_pages(struct flash_bank *bank, uint32_t start, uint32_t end, const uint8_t *buffer)
 {
        int res = ERROR_FAIL;
-       struct nrf5_info *chip = bank->driver_priv;
+       struct nrf5_bank *nbank = bank->driver_priv;
+       struct nrf5_info *chip = nbank->chip;
 
        assert(start % chip->code_page_size == 0);
        assert(end % chip->code_page_size == 0);
@@ -860,29 +882,41 @@ static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
                       uint32_t offset, uint32_t count)
 {
        int res;
+       struct nrf5_bank *nbank = bank->driver_priv;
        struct nrf5_info *chip;
 
        res = nrf5_get_probed_chip_if_halted(bank, &chip);
        if (res != ERROR_OK)
                return res;
 
-       return chip->bank[bank->bank_number].write(bank, chip, buffer, offset, count);
+       return nbank->write(bank, chip, buffer, offset, count);
 }
 
+static void nrf5_free_driver_priv(struct flash_bank *bank)
+{
+       struct nrf5_bank *nbank = bank->driver_priv;
+       struct nrf5_info *chip = nbank->chip;
+       if (chip == NULL)
+               return;
+
+       chip->refcount--;
+       if (chip->refcount == 0) {
+               free(chip);
+               bank->driver_priv = NULL;
+       }
+}
 
 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
 {
        static struct nrf5_info *chip;
+       struct nrf5_bank *nbank = NULL;
 
        switch (bank->base) {
        case NRF5_FLASH_BASE:
-               bank->bank_number = 0;
-               break;
        case NRF5_UICR_BASE:
-               bank->bank_number = 1;
                break;
        default:
-               LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base);
+               LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
                return ERROR_FAIL;
        }
 
@@ -897,15 +931,20 @@ FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
 
        switch (bank->base) {
        case NRF5_FLASH_BASE:
-               chip->bank[bank->bank_number].write = nrf5_code_flash_write;
+               nbank = &chip->bank[0];
+               nbank->write = nrf5_code_flash_write;
                break;
        case NRF5_UICR_BASE:
-               chip->bank[bank->bank_number].write = nrf5_uicr_flash_write;
+               nbank = &chip->bank[1];
+               nbank->write = nrf5_uicr_flash_write;
                break;
        }
+       assert(nbank != NULL);
 
-       chip->bank[bank->bank_number].probed = false;
-       bank->driver_priv = chip;
+       chip->refcount++;
+       nbank->chip = chip;
+       nbank->probed = false;
+       bank->driver_priv = nbank;
 
        return ERROR_OK;
 }
@@ -1093,6 +1132,7 @@ static const struct command_registration nrf5_exec_command_handlers[] = {
                .handler        = nrf5_handle_mass_erase_command,
                .mode           = COMMAND_EXEC,
                .help           = "Erase all flash contents of the chip.",
+               .usage          = "",
        },
        COMMAND_REGISTRATION_DONE
 };
@@ -1115,7 +1155,7 @@ static const struct command_registration nrf5_command_handlers[] = {
        COMMAND_REGISTRATION_DONE
 };
 
-struct flash_driver nrf5_flash = {
+const struct flash_driver nrf5_flash = {
        .name                   = "nrf5",
        .commands               = nrf5_command_handlers,
        .flash_bank_command     = nrf5_flash_bank_command,
@@ -1128,11 +1168,12 @@ struct flash_driver nrf5_flash = {
        .auto_probe             = nrf5_auto_probe,
        .erase_check            = default_flash_blank_check,
        .protect_check          = nrf5_protect_check,
+       .free_driver_priv       = nrf5_free_driver_priv,
 };
 
 /* We need to retain the flash-driver name as well as the commands
  * for backwards compatability */
-struct flash_driver nrf51_flash = {
+const struct flash_driver nrf51_flash = {
        .name                   = "nrf51",
        .commands               = nrf5_command_handlers,
        .flash_bank_command     = nrf5_flash_bank_command,
@@ -1145,4 +1186,5 @@ struct flash_driver nrf51_flash = {
        .auto_probe             = nrf5_auto_probe,
        .erase_check            = default_flash_blank_check,
        .protect_check          = nrf5_protect_check,
+       .free_driver_priv       = nrf5_free_driver_priv,
 };