uint32_t code_page_size;
uint32_t refcount;
- struct {
+ struct nrf5_bank {
+ struct nrf5_info *chip;
bool probed;
int (*write) (struct flash_bank *bank,
struct nrf5_info *chip,
.flash_size_kb = (fsize), \
}
-/* The known devices table below is derived from the "nRF51 Series
- * Compatibility Matrix" document, which can be found by searching for
- * ATTN-51 on the Nordic Semi website:
+/* The known devices table below is derived from the "nRF5x series
+ * compatibility matrix" documents, which can be found in the "DocLib" of
+ * nordic:
*
- * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
+ * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51422_ic_revision_overview
+ * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51822_ic_revision_overview
+ * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51824_ic_revision_overview
+ * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52810/latest/COMP/nrf52810/nRF52810_ic_revision_overview
+ * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52832/latest/COMP/nrf52832/ic_revision_overview
+ * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52840/latest/COMP/nrf52840/nRF52840_ic_revision_overview
*
* Up to date with Matrix v2.0, plus some additional HWIDs.
*
/* nRF52832 Devices */
NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512),
NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512),
+ NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512),
/* nRF52840 Devices */
NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024),
static int nrf5_bank_is_probed(struct flash_bank *bank)
{
- struct nrf5_info *chip = bank->driver_priv;
+ struct nrf5_bank *nbank = bank->driver_priv;
- assert(chip != NULL);
+ assert(nbank != NULL);
- return chip->bank[bank->bank_number].probed;
+ return nbank->probed;
}
static int nrf5_probe(struct flash_bank *bank);
return ERROR_TARGET_NOT_HALTED;
}
- *chip = bank->driver_priv;
+ struct nrf5_bank *nbank = bank->driver_priv;
+ *chip = nbank->chip;
int probed = nrf5_bank_is_probed(bank);
if (probed < 0)
{
uint32_t ready;
int res;
- int timeout_ms = 200;
+ int timeout_ms = 340;
int64_t ts_start = timeval_ms();
do {
if (bank->base == NRF5_UICR_BASE)
return ERROR_OK;
- struct nrf5_info *chip = bank->driver_priv;
+ struct nrf5_bank *nbank = bank->driver_priv;
+ struct nrf5_info *chip = nbank->chip;
assert(chip != NULL);
{
uint32_t hwid;
int res;
- struct nrf5_info *chip = bank->driver_priv;
+ struct nrf5_bank *nbank = bank->driver_priv;
+ struct nrf5_info *chip = nbank->chip;
res = target_read_u32(chip->target, NRF5_FICR_CONFIGID, &hwid);
if (res != ERROR_OK) {
static int nrf5_write_pages(struct flash_bank *bank, uint32_t start, uint32_t end, const uint8_t *buffer)
{
int res = ERROR_FAIL;
- struct nrf5_info *chip = bank->driver_priv;
+ struct nrf5_bank *nbank = bank->driver_priv;
+ struct nrf5_info *chip = nbank->chip;
assert(start % chip->code_page_size == 0);
assert(end % chip->code_page_size == 0);
uint32_t offset, uint32_t count)
{
int res;
+ struct nrf5_bank *nbank = bank->driver_priv;
struct nrf5_info *chip;
res = nrf5_get_probed_chip_if_halted(bank, &chip);
if (res != ERROR_OK)
return res;
- return chip->bank[bank->bank_number].write(bank, chip, buffer, offset, count);
+ return nbank->write(bank, chip, buffer, offset, count);
}
static void nrf5_free_driver_priv(struct flash_bank *bank)
{
- struct nrf5_info *chip = bank->driver_priv;
+ struct nrf5_bank *nbank = bank->driver_priv;
+ struct nrf5_info *chip = nbank->chip;
if (chip == NULL)
return;
FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
{
static struct nrf5_info *chip;
+ struct nrf5_bank *nbank = NULL;
switch (bank->base) {
case NRF5_FLASH_BASE:
- bank->bank_number = 0;
- break;
case NRF5_UICR_BASE:
- bank->bank_number = 1;
break;
default:
- LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base);
+ LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
return ERROR_FAIL;
}
switch (bank->base) {
case NRF5_FLASH_BASE:
- chip->bank[bank->bank_number].write = nrf5_code_flash_write;
+ nbank = &chip->bank[0];
+ nbank->write = nrf5_code_flash_write;
break;
case NRF5_UICR_BASE:
- chip->bank[bank->bank_number].write = nrf5_uicr_flash_write;
+ nbank = &chip->bank[1];
+ nbank->write = nrf5_uicr_flash_write;
break;
}
+ assert(nbank != NULL);
chip->refcount++;
- chip->bank[bank->bank_number].probed = false;
- bank->driver_priv = chip;
+ nbank->chip = chip;
+ nbank->probed = false;
+ bank->driver_priv = nbank;
return ERROR_OK;
}
.handler = nrf5_handle_mass_erase_command,
.mode = COMMAND_EXEC,
.help = "Erase all flash contents of the chip.",
+ .usage = "",
},
COMMAND_REGISTRATION_DONE
};
COMMAND_REGISTRATION_DONE
};
-struct flash_driver nrf5_flash = {
+const struct flash_driver nrf5_flash = {
.name = "nrf5",
.commands = nrf5_command_handlers,
.flash_bank_command = nrf5_flash_bank_command,
/* We need to retain the flash-driver name as well as the commands
* for backwards compatability */
-struct flash_driver nrf51_flash = {
+const struct flash_driver nrf51_flash = {
.name = "nrf51",
.commands = nrf5_command_handlers,
.flash_bank_command = nrf5_flash_bank_command,