nrf51: Add a known devices table and simple chip type detection code

[openocd.git] / src / flash / nor / nrf51.c

diff --git a/src/flash/nor/nrf51.c b/src/flash/nor/nrf51.c
index 79e6d49e6b205ba85876c4fc574acdab706672ef..7820baf5581cd728b2395d45d6a0464c93644e11 100644 (file)
--- a/src/flash/nor/nrf51.c
+++ b/src/flash/nor/nrf51.c
@@ -109,6 +109,91 @@ struct nrf51_info {
        struct target *target;
 };
 
+struct nrf51_device_spec {
+       uint16_t hwid;
+       const char *variant;
+       const char *build_code;
+       unsigned int flash_size_kb;
+};
+
+static const struct nrf51_device_spec nrf51_known_devices_table[] = {
+       {
+               .hwid           = 0x001D,
+               .variant        = "QFAA",
+               .build_code     = "CA/C0",
+               .flash_size_kb  = 256,
+       },
+       {
+               .hwid           = 0x002A,
+               .variant        = "QFAA",
+               .build_code     = "FA",
+               .flash_size_kb  = 256,
+       },
+       {
+               .hwid           = 0x0044,
+               .variant        = "QFAA",
+               .build_code     = "GC",
+               .flash_size_kb  = 256,
+       },
+       {
+               .hwid           = 0x003C,
+               .variant        = "QFAA",
+               .build_code     = "G0",
+               .flash_size_kb  = 256,
+       },
+
+       {
+               .hwid           = 0x0020,
+               .variant        = "CEAA",
+               .build_code     = "BA",
+               .flash_size_kb  = 256,
+       },
+       {
+               .hwid           = 0x002F,
+               .variant        = "CEAA",
+               .build_code     = "B0",
+               .flash_size_kb  = 256,
+       },
+       {
+               .hwid           = 0x0040,
+               .variant        = "CEAA",
+               .build_code     = "CA",
+               .flash_size_kb  = 256,
+       },
+       {
+               .hwid           = 0x0047,
+               .variant        = "CEAA",
+               .build_code     = "DA",
+               .flash_size_kb  = 256,
+       },
+       {
+               .hwid           = 0x004D,
+               .variant        = "CEAA",
+               .build_code     = "D0",
+               .flash_size_kb  = 256,
+       },
+
+       {
+               .hwid           = 0x0026,
+               .variant        = "QFAB",
+               .build_code     = "AA",
+               .flash_size_kb  = 128,
+       },
+       {
+               .hwid           = 0x0027,
+               .variant        = "QFAB",
+               .build_code     = "A0",
+               .flash_size_kb  = 128,
+       },
+       {
+               .hwid           = 0x004C,
+               .variant        = "QFAB",
+               .build_code     = "B0",
+               .flash_size_kb  = 128,
+       },
+
+};
+
 static int nrf51_probe(struct flash_bank *bank);
 
 static int nrf51_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf51_info **chip)
@@ -330,20 +415,32 @@ static int nrf51_protect(struct flash_bank *bank, int set, int first, int last)
 
 static int nrf51_probe(struct flash_bank *bank)
 {
-       uint32_t id;
+       uint32_t hwid;
        int res;
        struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
 
-       res = target_read_u32(chip->target, NRF51_FICR_DEVICEID0, &id);
+
+       res = target_read_u32(chip->target, NRF51_FICR_CONFIGID, &hwid);
        if (res != ERROR_OK) {
-               LOG_ERROR("Couldn't read Device ID 0 register");
+               LOG_ERROR("Couldn't read CONFIGID register");
                return res;
        }
 
-       res = target_read_u32(chip->target, NRF51_FICR_DEVICEID1, &id);
-       if (res != ERROR_OK) {
-               LOG_ERROR("Couldn't read Device ID 1 register");
-               return res;
+       hwid &= 0xFFFF; /* HWID is stored in the lower two
+                        * bytes of the CONFIGID register */
+
+       const struct nrf51_device_spec *spec = NULL;
+       for (size_t i = 0; i < ARRAY_SIZE(nrf51_known_devices_table); i++)
+               if (hwid == nrf51_known_devices_table[i].hwid) {
+                       spec = &nrf51_known_devices_table[i];
+                       break;
+               }
+
+       if (spec) {
+               LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
+                        spec->variant, spec->build_code, spec->flash_size_kb);
+       } else {
+               LOG_WARNING("Unknown device (HWID 0x%08" PRIx32 ")", hwid);
        }
 
        res = target_read_u32(chip->target, NRF51_FICR_CODEPAGESIZE,
@@ -360,6 +457,11 @@ static int nrf51_probe(struct flash_bank *bank)
                return res;
        }
 
+       if (spec && chip->code_memory_size != spec->flash_size_kb) {
+               LOG_ERROR("Chip's reported Flash capacity does not match expected one");
+               return ERROR_FAIL;
+       }
+
        bank->size = chip->code_memory_size * 1024;
        bank->num_sectors = bank->size / chip->code_page_size;
        bank->sectors = calloc(bank->num_sectors,
@@ -429,7 +531,7 @@ static int nrf51_erase_page(struct nrf51_info *chip, struct flash_sector *sector
        return res;
 }
 
-static int nrf51_write_page(struct flash_bank *bank, uint32_t offset, uint8_t *buffer)
+static int nrf51_write_page(struct flash_bank *bank, uint32_t offset, const uint8_t *buffer)
 {
        assert(offset % 4 == 0);
 
@@ -484,7 +586,7 @@ static int nrf51_erase(struct flash_bank *bank, int first, int last)
        return res;
 }
 
-static int nrf51_write(struct flash_bank *bank, uint8_t *buffer,
+static int nrf51_write(struct flash_bank *bank, const uint8_t *buffer,
                       uint32_t offset, uint32_t count)
 {
        int res;
@@ -502,7 +604,7 @@ static int nrf51_write(struct flash_bank *bank, uint8_t *buffer,
 
        struct {
                size_t   length;
-               uint8_t *buffer;
+               const uint8_t *buffer;
        }  start_extra, end_extra;
 
        start_extra.length      = region.start % chip->code_page_size;
@@ -717,11 +819,13 @@ static int nrf51_info(struct flash_bank *bank, char *buf, int buf_size)
                 "ram block 1 size: %"PRIu32"B\n"
                 "ram block 2 size: %"PRIu32"B\n"
                 "ram block 3 size: %"PRIu32 "B\n"
+                "config id: %" PRIx32 "\n"
+                "device id: 0x%"PRIx32"%08"PRIx32"\n"
                 "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
                 "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
                 "device address type: 0x%"PRIx32"\n"
                 "device address: 0x%"PRIx32"%08"PRIx32"\n"
-                "override enable: %"PRIu32"\n"
+                "override enable: %"PRIx32"\n"
                 "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
                 "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
                 "\n[user information control block]\n\n"
@@ -738,13 +842,15 @@ static int nrf51_info(struct flash_bank *bank, char *buf, int buf_size)
                 (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
                 (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
                 (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
-                ficr[9].value, ficr[9].value, ficr[9].value, ficr[9].value,
-                ficr[10].value, ficr[11].value, ficr[12].value, ficr[13].value,
-                ficr[14].value,
-                ficr[15].value, ficr[16].value,
-                ficr[17].value,
-                ficr[18].value, ficr[19].value, ficr[20].value, ficr[21].value, ficr[22].value,
-                ficr[23].value, ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value,
+                ficr[9].value,
+                ficr[10].value, ficr[11].value,
+                ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
+                ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
+                ficr[20].value,
+                ficr[21].value, ficr[22].value,
+                ficr[23].value,
+                ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
+                ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
                 (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
                 uicr[1].value & 0xFFFF,
                 uicr[2].value & 0xFF,