+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2016 - 2019 by Andreas Bolsch *
* andreas.bolsch@mni.thm.de *
* *
* Copyright (C) 2010 by Antonio Borneo *
* borneo.antonio@gmail.com *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
/* STM QuadSPI (QSPI) and OctoSPI (OCTOSPI) controller are SPI bus controllers
#endif
#include "imp.h"
+#include <helper/binarybuffer.h>
+#include <helper/bits.h>
#include <helper/time_support.h>
#include <target/algorithm.h>
#include <target/armv7m.h>
#undef SPIFLASH_READ
#undef SPIFLASH_PAGE_PROGRAM
-#define READ_REG(a) \
-({ \
- uint32_t _result; \
- \
- retval = target_read_u32(target, io_base + (a), &_result); \
- (retval == ERROR_OK) ? _result : 0x0; \
-})
-
/* saved mode settings */
#define QSPI_MODE (stmqspi_info->saved_ccr & \
(0xF0000000U | QSPI_DCYC_MASK | QSPI_4LINE_MODE | QSPI_ALTB_MODE | QSPI_ADDR4))
/* 4-byte address in octo mode, else 3-byte address for read SFDP */
#define OCTOSPI_CCR_READ_SFDP(len) \
((OCTOSPI_MODE_CCR & OCTOSPI_NO_DDTR & ~OCTOSPI_ADDR4 & OCTOSPI_NO_ALTB) | \
- ((len < 4) ? OCTOSPI_ADDR3 : OCTOSPI_ADDR4))
+ (((len) < 4) ? OCTOSPI_ADDR3 : OCTOSPI_ADDR4))
#define OCTOSPI_CCR_WRITE_ENABLE \
((OCTOSPI_MODE_CCR & OCTOSPI_NO_ADDR & OCTOSPI_NO_ALTB & OCTOSPI_NO_DATA))
#define SPI_ADSIZE (((stmqspi_info->saved_ccr >> SPI_ADSIZE_POS) & 0x3) + 1)
-#define OPI_CMD(cmd) ((OPI_MODE ? ((((uint16_t) cmd)<<8) | (~cmd & 0xFFU)) : cmd))
-
-#define OCTOSPI_CMD(mode, ccr, ir) \
-({ \
- retval = target_write_u32(target, io_base + OCTOSPI_CR, \
- OCTOSPI_MODE | mode); \
- if (retval == ERROR_OK) \
- retval = target_write_u32(target, io_base + OCTOSPI_TCR, \
- (stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK) | \
- ((OPI_MODE && (mode == OCTOSPI_READ_MODE)) ? \
- (OPI_DUMMY<<OCTOSPI_DCYC_POS) : 0)); \
- if (retval == ERROR_OK) \
- retval = target_write_u32(target, io_base + OCTOSPI_CCR, ccr); \
- if (retval == ERROR_OK) \
- retval = target_write_u32(target, io_base + OCTOSPI_IR, \
- OPI_CMD(ir)); \
- retval; \
-})
+#define OPI_CMD(cmd) ((OPI_MODE ? ((((uint16_t)(cmd)) << 8) | (~(cmd) & 0xFFU)) : (cmd)))
/* convert uint32_t into 4 uint8_t in little endian byte order */
static inline uint32_t h_to_le_32(uint32_t val)
{
uint32_t result;
- h_u32_to_le((uint8_t *) &result, val);
+ h_u32_to_le((uint8_t *)&result, val);
return result;
}
bool octo;
struct flash_device dev;
uint32_t io_base;
- uint32_t saved_cr; /* in particalar FSEL, DFM bit mask in QUADSPI_CR *AND* OCTOSPI_CR */
+ uint32_t saved_cr; /* in particular FSEL, DFM bit mask in QUADSPI_CR *AND* OCTOSPI_CR */
uint32_t saved_ccr; /* different meaning for QUADSPI and OCTOSPI */
uint32_t saved_tcr; /* only for OCTOSPI */
uint32_t saved_ir; /* only for OCTOSPI */
unsigned int sfdp_dummy2; /* number of dummy bytes for SFDP read for flash2 */
};
+static inline int octospi_cmd(struct flash_bank *bank, uint32_t mode,
+ uint32_t ccr, uint32_t ir)
+{
+ struct target *target = bank->target;
+ const struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
+ const uint32_t io_base = stmqspi_info->io_base;
+
+ int retval = target_write_u32(target, io_base + OCTOSPI_CR,
+ OCTOSPI_MODE | mode);
+
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_u32(target, io_base + OCTOSPI_TCR,
+ (stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK) |
+ ((OPI_MODE && (mode == OCTOSPI_READ_MODE)) ?
+ (OPI_DUMMY << OCTOSPI_DCYC_POS) : 0));
+
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_u32(target, io_base + OCTOSPI_CCR, ccr);
+
+ if (retval != ERROR_OK)
+ return retval;
+
+ return target_write_u32(target, io_base + OCTOSPI_IR, OPI_CMD(ir));
+}
+
FLASH_BANK_COMMAND_HANDLER(stmqspi_flash_bank_command)
{
struct stmqspi_flash_bank *stmqspi_info;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], io_base);
stmqspi_info = malloc(sizeof(struct stmqspi_flash_bank));
- if (stmqspi_info == NULL) {
+ if (!stmqspi_info) {
LOG_ERROR("not enough memory");
return ERROR_FAIL;
}
struct target *target = bank->target;
struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
uint32_t io_base = stmqspi_info->io_base;
- uint32_t spi_sr;
- int retval;
long long endtime;
endtime = timeval_ms() + timeout;
do {
- spi_sr = READ_REG(SPI_SR);
- if ((spi_sr & (1U<<SPI_BUSY)) == 0) {
- if (retval == ERROR_OK) {
- /* Clear transmit finished flag */
- retval = target_write_u32(target, io_base + SPI_FCR, (1U<<SPI_TCF));
- }
+ uint32_t spi_sr;
+ int retval = target_read_u32(target, io_base + SPI_SR, &spi_sr);
+
+ if (retval != ERROR_OK)
return retval;
+
+ if ((spi_sr & BIT(SPI_BUSY)) == 0) {
+ /* Clear transmit finished flag */
+ return target_write_u32(target, io_base + SPI_FCR, BIT(SPI_TCF));
} else
LOG_DEBUG("busy: 0x%08X", spi_sr);
alive_sleep(1);
return ERROR_FLASH_OPERATION_FAILED;
}
+static int stmqspi_abort(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ const struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
+ const uint32_t io_base = stmqspi_info->io_base;
+ uint32_t cr;
+
+ int retval = target_read_u32(target, io_base + SPI_CR, &cr);
+
+ if (retval != ERROR_OK)
+ cr = 0;
+
+ return target_write_u32(target, io_base + SPI_CR, cr | BIT(SPI_ABORT));
+}
+
/* Set to memory-mapped mode, e.g. after an error */
static int set_mm_mode(struct flash_bank *bank)
{
return retval;
/* Abort any previous operation */
- retval = target_write_u32(target, io_base + SPI_CR,
- READ_REG(SPI_CR) | (1U<<SPI_ABORT));
+ retval = stmqspi_abort(bank);
if (retval != ERROR_OK)
return retval;
int count, retval;
/* Abort any previous operation */
- retval = target_write_u32(target, io_base + SPI_CR,
- READ_REG(SPI_CR) | (1U<<SPI_ABORT));
+ retval = stmqspi_abort(bank);
if (retval != ERROR_OK)
return retval;
/* Read always two (for DTR mode) bytes per chip */
count = 2;
retval = target_write_u32(target, io_base + SPI_DLR,
- ((stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 2 * count : count) - 1);
+ ((stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 2 * count : count) - 1);
if (retval != ERROR_OK)
goto err;
/* Read status */
if (IS_OCTOSPI) {
- retval = OCTOSPI_CMD(OCTOSPI_READ_MODE, OCTOSPI_CCR_READ_STATUS, SPIFLASH_READ_STATUS);
+ retval = octospi_cmd(bank, OCTOSPI_READ_MODE, OCTOSPI_CCR_READ_STATUS,
+ SPIFLASH_READ_STATUS);
if (OPI_MODE) {
/* Dummy address 0, only required for 8-line mode */
retval = target_write_u32(target, io_base + SPI_AR, 0);
*status = 0;
/* for debugging only */
- (void) READ_REG(SPI_SR);
+ uint32_t dummy;
+ (void)target_read_u32(target, io_base + SPI_SR, &dummy);
for ( ; count > 0; --count) {
- if ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
- != (1U<<SPI_FSEL_FLASH)) {
+ if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
+ != BIT(SPI_FSEL_FLASH)) {
/* get status of flash 1 in dual mode or flash 1 only mode */
retval = target_read_u8(target, io_base + SPI_DR, &data);
if (retval != ERROR_OK)
*status |= data;
}
- if ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
- != (0U<<SPI_FSEL_FLASH)) {
+ if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) {
/* get status of flash 2 in dual mode or flash 2 only mode */
retval = target_read_u8(target, io_base + SPI_DR, &data);
if (retval != ERROR_OK)
goto err;
- *status |= ((uint16_t) data) << 8;
+ *status |= ((uint16_t)data) << 8;
}
}
int retval;
/* Abort any previous operation */
- retval = target_write_u32(target, io_base + SPI_CR,
- READ_REG(SPI_CR) | (1U<<SPI_ABORT));
+ retval = stmqspi_abort(bank);
if (retval != ERROR_OK)
return retval;
/* Send write enable command */
if (IS_OCTOSPI) {
- retval = OCTOSPI_CMD(OCTOSPI_WRITE_MODE, OCTOSPI_CCR_WRITE_ENABLE, SPIFLASH_WRITE_ENABLE);
+ retval = octospi_cmd(bank, OCTOSPI_WRITE_MODE, OCTOSPI_CCR_WRITE_ENABLE,
+ SPIFLASH_WRITE_ENABLE);
if (OPI_MODE) {
/* Dummy address 0, only required for 8-line mode */
retval = target_write_u32(target, io_base + SPI_AR, 0);
if (retval != ERROR_OK)
goto err;
}
- } else
+ } else
retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_WRITE_ENABLE);
if (retval != ERROR_OK)
goto err;
goto err;
/* Check write enabled for flash 1 */
- if (((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
- != (1U<<SPI_FSEL_FLASH)))
+ if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
+ != BIT(SPI_FSEL_FLASH))
if ((status & (SPIFLASH_WE_BIT | SPIFLASH_BSY_BIT)) != SPIFLASH_WE_BIT) {
- LOG_ERROR("Cannot write enable flash1. Status=0x%02" PRIx8,
- status & 0xFF);
+ LOG_ERROR("Cannot write enable flash1. Status=0x%02x",
+ status & 0xFFU);
return ERROR_FLASH_OPERATION_FAILED;
}
/* Check write enabled for flash 2 */
status >>= 8;
- if (((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
- != (0U<<SPI_FSEL_FLASH)))
+ if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0)
if ((status & (SPIFLASH_WE_BIT | SPIFLASH_BSY_BIT)) != SPIFLASH_WE_BIT) {
- LOG_ERROR("Cannot write enable flash2. Status=0x%02" PRIx8,
- status & 0xFF);
+ LOG_ERROR("Cannot write enable flash2. Status=0x%02x",
+ status & 0xFFU);
return ERROR_FLASH_OPERATION_FAILED;
}
return ERROR_COMMAND_SYNTAX_ERROR;
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
stmqspi_info = bank->driver_priv;
/* Send Mass Erase command */
if (IS_OCTOSPI)
- retval = OCTOSPI_CMD(OCTOSPI_WRITE_MODE, OCTOSPI_CCR_MASS_ERASE,
+ retval = octospi_cmd(bank, OCTOSPI_WRITE_MODE, OCTOSPI_CCR_MASS_ERASE,
stmqspi_info->dev.chip_erase_cmd);
else
retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_MASS_ERASE);
goto err;
/* Check for command in progress for flash 1 */
- if (((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
- != (1U<<SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
+ if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
+ != BIT(SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
((status & SPIFLASH_WE_BIT) != 0)) {
- LOG_ERROR("Mass erase command not accepted by flash1. Status=0x%02" PRIx8,
- status & 0xFF);
+ LOG_ERROR("Mass erase command not accepted by flash1. Status=0x%02x",
+ status & 0xFFU);
retval = ERROR_FLASH_OPERATION_FAILED;
goto err;
}
/* Check for command in progress for flash 2 */
status >>= 8;
- if (((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
- != (0U<<SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
+ if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) &&
+ ((status & SPIFLASH_BSY_BIT) == 0) &&
((status & SPIFLASH_WE_BIT) != 0)) {
- LOG_ERROR("Mass erase command not accepted by flash2. Status=0x%02" PRIx8,
- status & 0xFF);
+ LOG_ERROR("Mass erase command not accepted by flash2. Status=0x%02x",
+ status & 0xFFU);
retval = ERROR_FLASH_OPERATION_FAILED;
goto err;
}
retval = wait_till_ready(bank, SPI_MASS_ERASE_TIMEOUT);
duration_measure(&bench);
- if (retval == ERROR_OK) {
- /* set all sectors as erased */
- for (sector = 0; sector < bank->num_sectors; sector++)
- bank->sectors[sector].is_erased = 1;
-
+ if (retval == ERROR_OK)
command_print(CMD, "stmqspi mass erase completed in %fs (%0.3f KiB/s)",
duration_elapsed(&bench),
duration_kbps(&bench, bank->size));
- } else {
+ else
command_print(CMD, "stmqspi mass erase not completed even after %fs",
duration_elapsed(&bench));
- }
err:
/* Switch to memory mapped mode before return to prompt */
int result;
for (result = 0; (unsigned int) result < sizeof(uint32_t) * CHAR_BIT; result++)
- if (word == (1UL<<result))
+ if (word == BIT(result))
return result;
return -1;
LOG_DEBUG("%s", __func__);
- dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
+ dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
/* chip_erase_cmd, sectorsize and erase_cmd are optional */
if ((CMD_ARGC < 7) || (CMD_ARGC > 10))
return ERROR_COMMAND_SYNTAX_ERROR;
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, index++, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
target = bank->target;
bank->size = stmqspi_info->dev.size_in_bytes << dual;
io_base = stmqspi_info->io_base;
- fsize = (READ_REG(SPI_DCR)>>SPI_FSIZE_POS) & ((1U<<SPI_FSIZE_LEN) - 1);
+
+ uint32_t dcr;
+ retval = target_read_u32(target, io_base + SPI_DCR, &dcr);
+
if (retval != ERROR_OK)
return retval;
+ fsize = (dcr >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
+
LOG_DEBUG("FSIZE = 0x%04x", fsize);
- if (bank->size == (1U<<(fsize + 1)))
+ if (bank->size == BIT(fsize + 1))
LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
- else if (bank->size == (1U<<(fsize + 0)))
+ else if (bank->size == BIT(fsize + 0))
LOG_DEBUG("FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?");
else
LOG_ERROR("FSIZE in DCR(1) doesn't match actual capacity.");
bank->num_sectors =
stmqspi_info->dev.size_in_bytes / stmqspi_info->dev.sectorsize;
sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
- if (sectors == NULL) {
+ if (!sectors) {
LOG_ERROR("not enough memory");
return ERROR_FAIL;
}
LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 "kbytes,"
" bank size = %" PRIu32 "kbytes", stmqspi_info->dev.name,
stmqspi_info->dev.size_in_bytes / 1024,
- (stmqspi_info->dev.size_in_bytes / 1024)<<dual);
+ (stmqspi_info->dev.size_in_bytes / 1024) << dual);
else
LOG_INFO("flash \'%s\' id = unknown\nchip size = %" PRIu32 "bytes,"
" bank size = %" PRIu32 "bytes", stmqspi_info->dev.name,
stmqspi_info->dev.size_in_bytes,
- stmqspi_info->dev.size_in_bytes<<dual);
+ stmqspi_info->dev.size_in_bytes << dual);
stmqspi_info->probed = true;
}
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
target = bank->target;
if (num_read == 0) {
/* nothing to read, then one command byte and for dual flash
* an *even* number of data bytes to follow */
- if (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) {
+ if (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) {
if ((num_write & 1) == 0) {
LOG_ERROR("number of data bytes to write must be even in dual mode");
return ERROR_COMMAND_SYNTAX_ERROR;
}
} else {
/* read mode, one command byte and up to four following address bytes */
- if (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) {
+ if (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) {
if ((num_read & 1) != 0) {
LOG_ERROR("number of bytes to read must be even in dual mode");
return ERROR_COMMAND_SYNTAX_ERROR;
}
/* Abort any previous operation */
- retval = target_write_u32(target, io_base + SPI_CR,
- READ_REG(SPI_CR) | (1U<<SPI_ABORT));
+ retval = stmqspi_abort(bank);
if (retval != ERROR_OK)
return retval;
snprintf(output, sizeof(output), "spi: %02x ", cmd_byte);
if (num_read == 0) {
/* write, send cmd byte */
- retval = target_write_u32(target, io_base + SPI_DLR, ((uint32_t) num_write) - 2);
+ retval = target_write_u32(target, io_base + SPI_DLR, ((uint32_t)num_write) - 2);
if (retval != ERROR_OK)
goto err;
if (IS_OCTOSPI)
- retval = OCTOSPI_CMD(OCTOSPI_WRITE_MODE,
+ retval = octospi_cmd(bank, OCTOSPI_WRITE_MODE,
(OCTOSPI_MODE_CCR & OCTOSPI_NO_ALTB & OCTOSPI_NO_ADDR &
((num_write == 1) ? OCTOSPI_NO_DATA : ~0U)), cmd_byte);
else
for (count = 3; count < CMD_ARGC; count++) {
COMMAND_PARSE_NUMBER(u8, CMD_ARGV[count], data);
snprintf(temp, sizeof(temp), "%02" PRIx8 " ", data);
- retval = target_write_u8(target, io_base + SPI_DR, data); \
+ retval = target_write_u8(target, io_base + SPI_DR, data);
if (retval != ERROR_OK)
goto err;
strncat(output, temp, sizeof(output) - strlen(output) - 1);
strncat(output, "-> ", sizeof(output) - strlen(output) - 1);
/* send cmd byte, if ADMODE indicates no address, this already triggers command */
- retval = target_write_u32(target, io_base + SPI_DLR, ((uint32_t) num_read) - 1);
+ retval = target_write_u32(target, io_base + SPI_DLR, ((uint32_t)num_read) - 1);
if (retval != ERROR_OK)
goto err;
if (IS_OCTOSPI)
- retval = OCTOSPI_CMD(OCTOSPI_READ_MODE,
+ retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
(OCTOSPI_MODE_CCR & OCTOSPI_NO_DDTR & OCTOSPI_NO_ALTB & ~OCTOSPI_ADDR4 &
((num_write == 1) ? OCTOSPI_NO_ADDR : ~0U)) |
- (((num_write - 2) & 0x3U)<<SPI_ADSIZE_POS), cmd_byte);
+ (((num_write - 2) & 0x3U) << SPI_ADSIZE_POS), cmd_byte);
else
retval = target_write_u32(target, io_base + QSPI_CCR,
(QSPI_MODE & ~QSPI_DCYC_MASK & QSPI_NO_ALTB & ~QSPI_ADDR4 &
((num_write == 1) ? QSPI_NO_ADDR : ~0U)) |
- ((QSPI_READ_MODE | (((num_write - 2) & 0x3U)<<SPI_ADSIZE_POS) | cmd_byte)));
+ ((QSPI_READ_MODE | (((num_write - 2) & 0x3U) << SPI_ADSIZE_POS) | cmd_byte)));
if (retval != ERROR_OK)
goto err;
/* Send Sector Erase command */
if (IS_OCTOSPI)
- retval = OCTOSPI_CMD(OCTOSPI_WRITE_MODE, OCTOSPI_CCR_SECTOR_ERASE,
+ retval = octospi_cmd(bank, OCTOSPI_WRITE_MODE, OCTOSPI_CCR_SECTOR_ERASE,
stmqspi_info->dev.erase_cmd);
else
retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_SECTOR_ERASE);
/* Check for command in progress for flash 1 */
/* If BSY and WE are already cleared the erase did probably complete already */
- if (((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
- != (1U<<SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
+ if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
+ != BIT(SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
((status & SPIFLASH_WE_BIT) != 0)) {
- LOG_ERROR("Sector erase command not accepted by flash1. Status=0x%02" PRIx8,
- status & 0xFF);
+ LOG_ERROR("Sector erase command not accepted by flash1. Status=0x%02x",
+ status & 0xFFU);
retval = ERROR_FLASH_OPERATION_FAILED;
goto err;
}
/* Check for command in progress for flash 2 */
/* If BSY and WE are already cleared the erase did probably complete already */
status >>= 8;
- if (((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) | (1U<<SPI_FSEL_FLASH)))
- != (0U<<SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
+ if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) &&
+ ((status & SPIFLASH_BSY_BIT) == 0) &&
((status & SPIFLASH_WE_BIT) != 0)) {
- LOG_ERROR("Sector erase command not accepted by flash2. Status=0x%02" PRIx8,
- status & 0xFF);
+ LOG_ERROR("Sector erase command not accepted by flash2. Status=0x%02x",
+ status & 0xFFU);
retval = ERROR_FLASH_OPERATION_FAILED;
goto err;
}
{
struct target *target = bank->target;
struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
- uint32_t io_base = stmqspi_info->io_base;
struct duration bench;
struct reg_param reg_params[2];
struct armv7m_algorithm armv7m_info;
}
/* Abort any previous operation */
- retval = target_write_u32(target, io_base + SPI_CR,
- READ_REG(SPI_CR) | (1U<<SPI_ABORT));
+ retval = stmqspi_abort(bank);
if (retval != ERROR_OK)
return retval;
/* prepare QSPI/OCTOSPI_CCR register values */
retval = target_write_buffer(target, algorithm->address
+ codesize - sizeof(ccr_buffer),
- sizeof(ccr_buffer), (uint8_t *) ccr_buffer);
+ sizeof(ccr_buffer), (uint8_t *)ccr_buffer);
if (retval != ERROR_OK)
goto err;
retval = target_write_buffer(target, algorithm->address
+ codesize + index * sizeof(erase_check_info),
- sizeof(erase_check_info), (uint8_t *) &erase_check_info);
+ sizeof(erase_check_info), (uint8_t *)&erase_check_info);
if (retval != ERROR_OK)
goto err;
}
for (index = 0; index < count; index++) {
retval = target_read_buffer(target, algorithm->address
+ codesize + index * sizeof(erase_check_info),
- sizeof(erase_check_info), (uint8_t *) &erase_check_info);
+ sizeof(erase_check_info), (uint8_t *)&erase_check_info);
if (retval != ERROR_OK)
goto err;
/* we need le_32_to_h, but that's the same as h_to_le_32 */
result = h_to_le_32(erase_check_info.result);
bank->sectors[sector + index].is_erased = ((result & 0xFF) == 0xFF);
- LOG_DEBUG("Flash sector %u checked: 0x%04" PRIx16, sector + index, result & 0xFFFF);
+ LOG_DEBUG("Flash sector %u checked: 0x%04x", sector + index, result & 0xFFFFU);
}
keep_alive();
sector += count;
pagesize = SPIFLASH_DEF_PAGESIZE;
/* adjust size according to dual flash mode */
- pagesize = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? pagesize << 1 : pagesize;
+ pagesize = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? pagesize << 1 : pagesize;
/* This will overlay the last 4 words of stmqspi/stmoctospi_crc32_code in target */
/* for read use the saved settings (memory mapped mode) but indirect read mode */
/* prepare QSPI/OCTOSPI_CCR register values */
retval = target_write_buffer(target, algorithm->address
+ codesize - sizeof(ccr_buffer),
- sizeof(ccr_buffer), (uint8_t *) ccr_buffer);
+ sizeof(ccr_buffer), (uint8_t *)ccr_buffer);
if (retval != ERROR_OK)
goto err;
LOG_DEBUG("%s: offset=0x%08" PRIx32 " len=0x%08" PRIx32,
__func__, offset, count);
- dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
+ dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
/* see contrib/loaders/flash/stmqspi/stmqspi_read.S for src */
static const uint8_t stmqspi_read_code[] = {
h_to_le_32(OCTOSPI_MODE | OCTOSPI_READ_MODE),
h_to_le_32(IS_OCTOSPI ? OCTOSPI_CCR_READ_STATUS : QSPI_CCR_READ_STATUS),
h_to_le_32((stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK) |
- (OPI_MODE ? (OPI_DUMMY<<OCTOSPI_DCYC_POS) : 0)),
+ (OPI_MODE ? (OPI_DUMMY << OCTOSPI_DCYC_POS) : 0)),
h_to_le_32(OPI_CMD(SPIFLASH_READ_STATUS)),
},
{
/* prepare QSPI/OCTOSPI_CCR register values */
retval = target_write_buffer(target, algorithm->address
+ codesize - sizeof(ccr_buffer),
- sizeof(ccr_buffer), (uint8_t *) ccr_buffer);
+ sizeof(ccr_buffer), (uint8_t *)ccr_buffer);
if (retval != ERROR_OK)
goto err;
{
struct target *target = bank->target;
struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
- uint32_t io_base = stmqspi_info->io_base;
int retval;
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
}
/* Abort any previous operation */
- retval = target_write_u32(target, io_base + SPI_CR,
- READ_REG(SPI_CR) | (1U<<SPI_ABORT));
+ retval = stmqspi_abort(bank);
if (retval != ERROR_OK)
return retval;
{
struct target *target = bank->target;
struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
- uint32_t io_base = stmqspi_info->io_base;
unsigned int dual, sector;
bool octal_dtr;
int retval;
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
__func__, offset, count);
- dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
- octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & (1U<<OCTOSPI_DDTR));
+ dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
+ octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
for (sector = 0; sector < bank->num_sectors; sector++) {
/* Start offset in or before this sector? */
/* End offset in or behind this sector? */
- if ((offset < (bank->sectors[sector].offset + bank->sectors[sector].size))
- && ((offset + count - 1) >= bank->sectors[sector].offset)
- && bank->sectors[sector].is_protected) {
+ if ((offset < (bank->sectors[sector].offset + bank->sectors[sector].size)) &&
+ ((offset + count - 1) >= bank->sectors[sector].offset) &&
+ bank->sectors[sector].is_protected) {
LOG_ERROR("Flash sector %u protected", sector);
return ERROR_FLASH_PROTECTED;
}
}
/* Abort any previous operation */
- retval = target_write_u32(target, io_base + SPI_CR,
- READ_REG(SPI_CR) | (1U<<SPI_ABORT));
+ retval = stmqspi_abort(bank);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- return qspi_read_write_block(bank, (uint8_t *) buffer, offset, count, true);
+ return qspi_read_write_block(bank, (uint8_t *)buffer, offset, count, true);
}
static int stmqspi_verify(struct flash_bank *bank, const uint8_t *buffer,
{
struct target *target = bank->target;
struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
- uint32_t io_base = stmqspi_info->io_base;
unsigned int dual;
bool octal_dtr;
int retval;
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
__func__, offset, count);
- dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
- octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & (1U<<OCTOSPI_DDTR));
+ dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
+ octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
}
/* Abort any previous operation */
- retval = target_write_u32(target, io_base + SPI_CR,
- READ_REG(SPI_CR) | (1U<<SPI_ABORT));
+ retval = stmqspi_abort(bank);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- return qspi_verify(bank, (uint8_t *) buffer, offset, count);
+ return qspi_verify(bank, (uint8_t *)buffer, offset, count);
}
/* Find appropriate dummy setting, in particular octo mode */
uint32_t io_base = stmqspi_info->io_base;
uint8_t data;
unsigned int dual, count;
- bool flash1 = !(stmqspi_info->saved_cr & (1U<<SPI_FSEL_FLASH));
+ bool flash1 = !(stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH));
int retval;
const unsigned int max_bytes = 64;
- dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
+ dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
LOG_DEBUG("%s: len=%d, dual=%u, flash1=%d",
__func__, len, dual, flash1);
/* Abort any previous operation */
retval = target_write_u32(target, io_base + SPI_CR,
- stmqspi_info->saved_cr | (1U<<SPI_ABORT));
+ stmqspi_info->saved_cr | BIT(SPI_ABORT));
if (retval != ERROR_OK)
goto err;
/* Read SFDP block */
if (IS_OCTOSPI)
- retval = OCTOSPI_CMD(OCTOSPI_READ_MODE, OCTOSPI_CCR_READ_SFDP(len),
- SPIFLASH_READ_SFDP);
+ retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
+ OCTOSPI_CCR_READ_SFDP(len), SPIFLASH_READ_SFDP);
else
retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_SFDP);
if (retval != ERROR_OK)
err:
/* Abort operation */
- retval = target_write_u32(target, io_base + SPI_CR,
- READ_REG(SPI_CR) | (1U<<SPI_ABORT));
+ retval = stmqspi_abort(bank);
return retval;
}
struct target *target = bank->target;
struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
uint32_t io_base = stmqspi_info->io_base;
- bool flash1 = !(stmqspi_info->saved_cr & (1U<<SPI_FSEL_FLASH));
+ bool flash1 = !(stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH));
unsigned int dual, count, len, *dummy;
int retval;
- dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
+ dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
if (IS_OCTOSPI && (((stmqspi_info->saved_ccr >> SPI_DMODE_POS) & 0x7) > 3)) {
/* in OCTO mode 4-byte address and (yet) unknown number of dummy clocks */
len = 3;
/* use sfdp_dummy1/2 according to currently selected flash */
- dummy = (stmqspi_info->saved_cr & (1U<<SPI_FSEL_FLASH)) ?
+ dummy = (stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH)) ?
&stmqspi_info->sfdp_dummy2 : &stmqspi_info->sfdp_dummy1;
/* according to SFDP standard, there should always be 8 dummy *CLOCKS*
/* Abort any previous operation */
retval = target_write_u32(target, io_base + SPI_CR,
- stmqspi_info->saved_cr | (1U<<SPI_ABORT));
+ stmqspi_info->saved_cr | BIT(SPI_ABORT));
if (retval != ERROR_OK)
goto err;
/* Read SFDP block */
if (IS_OCTOSPI)
- retval = OCTOSPI_CMD(OCTOSPI_READ_MODE, OCTOSPI_CCR_READ_SFDP(len),
- SPIFLASH_READ_SFDP);
+ retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
+ OCTOSPI_CCR_READ_SFDP(len), SPIFLASH_READ_SFDP);
else
retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_SFDP);
if (retval != ERROR_OK)
/* dummy clocks */
for (count = *dummy << dual; count > 0; --count) {
- retval = target_read_u8(target, io_base + SPI_DR, (uint8_t *) buffer);
+ retval = target_read_u8(target, io_base + SPI_DR, (uint8_t *)buffer);
if (retval != ERROR_OK)
goto err;
}
LOG_DEBUG("raw SFDP data 0x%08" PRIx32, *buffer);
/* endian correction, sfdp data is always le uint32_t based */
- *buffer = le_to_h_u32((uint8_t *) buffer);
+ *buffer = le_to_h_u32((uint8_t *)buffer);
buffer++;
}
uint32_t io_base = stmqspi_info->io_base;
uint8_t byte;
unsigned int type, count, len1, len2;
- int retval;
+ int retval = ERROR_OK;
/* invalidate both ids */
*id1 = 0;
/* SPIFLASH_READ_MID causes device in octal mode to go berserk, so don't use in this case */
for (type = (IS_OCTOSPI && OPI_MODE) ? 1 : 0; type < 2 ; type++) {
/* Abort any previous operation */
- retval = target_write_u32(target, io_base + SPI_CR,
- READ_REG(SPI_CR) | (1U<<SPI_ABORT));
+ retval = stmqspi_abort(bank);
if (retval != ERROR_OK)
goto err;
/* Read at most 16 bytes per chip */
count = 16;
retval = target_write_u32(target, io_base + SPI_DLR,
- (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH) ? count * 2 : count) - 1);
+ (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH) ? count * 2 : count) - 1);
if (retval != ERROR_OK)
goto err;
switch (type) {
case 0:
if (IS_OCTOSPI)
- retval = OCTOSPI_CMD(OCTOSPI_READ_MODE, OCTOSPI_CCR_READ_MID, SPIFLASH_READ_MID);
+ retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
+ OCTOSPI_CCR_READ_MID, SPIFLASH_READ_MID);
else
retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_MID);
break;
case 1:
if (IS_OCTOSPI)
- retval = OCTOSPI_CMD(OCTOSPI_READ_MODE, OCTOSPI_CCR_READ_ID, SPIFLASH_READ_ID);
+ retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
+ OCTOSPI_CCR_READ_ID, SPIFLASH_READ_ID);
else
retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_ID);
break;
}
/* for debugging only */
- (void) READ_REG(SPI_SR);
+ uint32_t dummy;
+ (void)target_read_u32(target, io_base + SPI_SR, &dummy);
/* Read ID from Data Register */
for (len1 = 0, len2 = 0; count > 0; --count) {
- if ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) |
- (1U<<SPI_FSEL_FLASH))) != (1U<<SPI_FSEL_FLASH)) {
+ if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
+ BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) {
retval = target_read_u8(target, io_base + SPI_DR, &byte);
if (retval != ERROR_OK)
goto err;
/* collect 3 bytes without continuation codes */
if ((byte != 0x7F) && (len1 < 3)) {
- *id1 = (*id1 >> 8) | ((uint32_t) byte) << 16;
+ *id1 = (*id1 >> 8) | ((uint32_t)byte) << 16;
len1++;
}
}
- if ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) |
- (1U<<SPI_FSEL_FLASH))) != 0) {
+ if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
+ BIT(SPI_FSEL_FLASH))) != 0) {
retval = target_read_u8(target, io_base + SPI_DR, &byte);
if (retval != ERROR_OK)
goto err;
/* collect 3 bytes without continuation codes */
if ((byte != 0x7F) && (len2 < 3)) {
- *id2 = (*id2 >> 8) | ((uint32_t) byte) << 16;
+ *id2 = (*id2 >> 8) | ((uint32_t)byte) << 16;
len2++;
}
}
break;
}
- if ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) |
- (1U<<SPI_FSEL_FLASH))) != (1U<<SPI_FSEL_FLASH)) {
+ if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
+ BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) {
if ((*id1 == 0x000000) || (*id1 == 0xFFFFFF)) {
/* no id retrieved, so id must be set manually */
LOG_INFO("No id from flash1");
}
}
- if ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) |
- (1U<<SPI_FSEL_FLASH))) != (0U<<SPI_FSEL_FLASH)) {
+ if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) {
if ((*id2 == 0x000000) || (*id2 == 0xFFFFFF)) {
/* no id retrieved, so id must be set manually */
LOG_INFO("No id from flash2");
if (stmqspi_info->probed) {
bank->size = 0;
bank->num_sectors = 0;
- if (bank->sectors)
- free(bank->sectors);
+ free(bank->sectors);
bank->sectors = NULL;
memset(&stmqspi_info->dev, 0, sizeof(stmqspi_info->dev));
stmqspi_info->sfdp_dummy1 = 0;
}
/* Abort any previous operation */
- retval = target_write_u32(target, io_base + SPI_CR,
- READ_REG(SPI_CR) | (1U<<SPI_ABORT));
+ retval = stmqspi_abort(bank);
if (retval != ERROR_OK)
return retval;
if (data == magic) {
LOG_DEBUG("QSPI_ABR register present");
stmqspi_info->octo = false;
- } else if (READ_REG(OCTOSPI_MAGIC) == OCTO_MAGIC_ID) {
- LOG_DEBUG("OCTOSPI_MAGIC present");
- stmqspi_info->octo = true;
} else {
- LOG_ERROR("No QSPI, no OCTOSPI at 0x%08" PRIx32, io_base);
- stmqspi_info->probed = false;
- stmqspi_info->dev.name = "none";
- return ERROR_FAIL;
+ uint32_t magic_id;
+
+ retval = target_read_u32(target, io_base + OCTOSPI_MAGIC, &magic_id);
+
+ if (retval == ERROR_OK && magic_id == OCTO_MAGIC_ID) {
+ LOG_DEBUG("OCTOSPI_MAGIC present");
+ stmqspi_info->octo = true;
+ } else {
+ LOG_ERROR("No QSPI, no OCTOSPI at 0x%08" PRIx32, io_base);
+ stmqspi_info->probed = false;
+ stmqspi_info->dev.name = "none";
+ return ERROR_FAIL;
+ }
}
/* save current FSEL and DFM bits in QSPI/OCTOSPI_CR, current QSPI/OCTOSPI_CCR value */
- stmqspi_info->saved_cr = READ_REG(SPI_CR);
+ retval = target_read_u32(target, io_base + SPI_CR, &stmqspi_info->saved_cr);
if (retval == ERROR_OK)
- stmqspi_info->saved_ccr = READ_REG(SPI_CCR);
+ retval = target_read_u32(target, io_base + SPI_CCR, &stmqspi_info->saved_ccr);
if (IS_OCTOSPI) {
- uint32_t mtyp;
+ uint32_t dcr1;
+
+ retval = target_read_u32(target, io_base + OCTOSPI_DCR1, &dcr1);
- mtyp = ((READ_REG(OCTOSPI_DCR1) & OCTOSPI_MTYP_MASK))>>OCTOSPI_MTYP_POS;
if (retval == ERROR_OK)
- stmqspi_info->saved_tcr = READ_REG(OCTOSPI_TCR);
+ retval = target_read_u32(target, io_base + OCTOSPI_TCR,
+ &stmqspi_info->saved_tcr);
+
if (retval == ERROR_OK)
- stmqspi_info->saved_ir = READ_REG(OCTOSPI_IR);
+ retval = target_read_u32(target, io_base + OCTOSPI_IR,
+ &stmqspi_info->saved_ir);
+
+ if (retval != ERROR_OK) {
+ LOG_ERROR("No OCTOSPI at io_base 0x%08" PRIx32, io_base);
+ stmqspi_info->probed = false;
+ stmqspi_info->dev.name = "none";
+ return ERROR_FAIL;
+ }
+
+ const uint32_t mtyp = (dcr1 & OCTOSPI_MTYP_MASK) >> OCTOSPI_MTYP_POS;
+
if ((mtyp != 0x0) && (mtyp != 0x1)) {
- retval = ERROR_FAIL;
LOG_ERROR("Only regular SPI protocol supported in OCTOSPI");
- }
- if (retval == ERROR_OK) {
- LOG_DEBUG("OCTOSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", OCTOSPI_CR 0x%08"
- PRIx32 ", OCTOSPI_CCR 0x%08" PRIx32 ", %d-byte addr", bank->base, io_base,
- stmqspi_info->saved_cr, stmqspi_info->saved_ccr, SPI_ADSIZE);
- } else {
- LOG_ERROR("No OCTOSPI at io_base 0x%08" PRIx32, io_base);
stmqspi_info->probed = false;
stmqspi_info->dev.name = "none";
return ERROR_FAIL;
}
+
+ LOG_DEBUG("OCTOSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", OCTOSPI_CR 0x%08"
+ PRIx32 ", OCTOSPI_CCR 0x%08" PRIx32 ", %d-byte addr", bank->base, io_base,
+ stmqspi_info->saved_cr, stmqspi_info->saved_ccr, SPI_ADSIZE);
} else {
if (retval == ERROR_OK) {
LOG_DEBUG("QSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", QSPI_CR 0x%08"
}
}
- dual = (stmqspi_info->saved_cr & (1U<<SPI_DUAL_FLASH)) ? 1 : 0;
- octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & (1U<<OCTOSPI_DDTR));
+ dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
+ octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
if (dual || octal_dtr)
bank->write_start_alignment = bank->write_end_alignment = 2;
else
uint32_t saved_cr = stmqspi_info->saved_cr;
/* select flash1 */
- stmqspi_info->saved_cr = stmqspi_info->saved_cr & ~(1U<<SPI_FSEL_FLASH);
+ stmqspi_info->saved_cr = stmqspi_info->saved_cr & ~BIT(SPI_FSEL_FLASH);
retval = spi_sfdp(bank, &temp, &read_sfdp_block);
/* restore saved_cr */
uint32_t saved_cr = stmqspi_info->saved_cr;
/* select flash2 */
- stmqspi_info->saved_cr = stmqspi_info->saved_cr | (1U<<SPI_FSEL_FLASH);
+ stmqspi_info->saved_cr = stmqspi_info->saved_cr | BIT(SPI_FSEL_FLASH);
retval = spi_sfdp(bank, &temp, &read_sfdp_block);
/* restore saved_cr */
/* Set correct size value */
bank->size = stmqspi_info->dev.size_in_bytes << dual;
- fsize = ((READ_REG(SPI_DCR)>>SPI_FSIZE_POS) & ((1U<<SPI_FSIZE_LEN) - 1));
+ uint32_t dcr;
+ retval = target_read_u32(target, io_base + SPI_DCR, &dcr);
+
if (retval != ERROR_OK)
goto err;
+ fsize = (dcr >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
+
LOG_DEBUG("FSIZE = 0x%04x", fsize);
- if (bank->size == (1U<<(fsize + 1)))
+ if (bank->size == BIT((fsize + 1)))
LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
- else if (bank->size == (1U<<(fsize + 0)))
+ else if (bank->size == BIT((fsize + 0)))
LOG_DEBUG("FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?");
else
LOG_ERROR("FSIZE in DCR(1) doesn't match actual capacity.");
/* create and fill sectors array */
bank->num_sectors = stmqspi_info->dev.size_in_bytes / stmqspi_info->dev.sectorsize;
sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
- if (sectors == NULL) {
+ if (!sectors) {
LOG_ERROR("not enough memory");
retval = ERROR_FAIL;
goto err;
return ERROR_OK;
}
-static int get_stmqspi_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_stmqspi_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
if (!(stmqspi_info->probed)) {
- snprintf(buf, buf_size,
- "\nQSPI flash bank not probed yet\n");
+ command_print_sameline(cmd, "\nQSPI flash bank not probed yet\n");
return ERROR_FLASH_BANK_NOT_PROBED;
}
- snprintf(buf, buf_size, "flash%s%s \'%s\', device id = 0x%06" PRIx32
+ command_print_sameline(cmd, "flash%s%s \'%s\', device id = 0x%06" PRIx32
", flash size = %" PRIu32 "%sbytes\n(page size = %" PRIu32
", read = 0x%02" PRIx8 ", qread = 0x%02" PRIx8
", pprog = 0x%02" PRIx8 ", mass_erase = 0x%02" PRIx8
", sector size = %" PRIu32 "%sbytes, sector_erase = 0x%02" PRIx8 ")",
- ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) |
- (1U<<SPI_FSEL_FLASH))) != (1U<<SPI_FSEL_FLASH)) ? "1" : "",
- ((stmqspi_info->saved_cr & ((1U<<SPI_DUAL_FLASH) |
- (1U<<SPI_FSEL_FLASH))) != (0U<<SPI_FSEL_FLASH)) ? "2" : "",
+ ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
+ BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) ? "1" : "",
+ ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
+ BIT(SPI_FSEL_FLASH))) != 0) ? "2" : "",
stmqspi_info->dev.name, stmqspi_info->dev.device_id,
bank->size / 4096 ? bank->size / 1024 : bank->size,
bank->size / 4096 ? "k" : "", stmqspi_info->dev.pagesize,
Code Review / openocd.git / blobdiff