* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
-
/* Flash registers */
#define FLASH_CR0 0x00000000
#define FLASH_ERR 0x00000001
-struct str7x_flash_bank
-{
+struct str7x_flash_bank {
uint32_t *sector_bits;
uint32_t disable_bit;
uint32_t busy_bits;
uint32_t register_base;
- struct working_area *write_algorithm;
};
struct str7x_mem_layout {
uint32_t sector_bit;
};
-enum str7x_status_codes
-{
+enum str7x_status_codes {
STR7X_CMD_SUCCESS = 0,
STR7X_INVALID_COMMAND = 1,
STR7X_SRC_ADDR_ERROR = 2,
STR7X_BUSY = 11
};
-static struct str7x_mem_layout mem_layout_str7bank0[] = {
+static const struct str7x_mem_layout mem_layout_str7bank0[] = {
{0x00000000, 0x02000, 0x01},
{0x00002000, 0x02000, 0x02},
{0x00004000, 0x02000, 0x04},
{0x00030000, 0x10000, 0x80}
};
-static struct str7x_mem_layout mem_layout_str7bank1[] = {
+static const struct str7x_mem_layout mem_layout_str7bank1[] = {
{0x00000000, 0x02000, 0x10000},
{0x00002000, 0x02000, 0x20000}
};
static int str7x_get_flash_adr(struct flash_bank *bank, uint32_t reg)
{
struct str7x_flash_bank *str7x_info = bank->driver_priv;
- return (str7x_info->register_base | reg);
+ return str7x_info->register_base | reg;
}
static int str7x_build_block_list(struct flash_bank *bank)
int num_sectors;
int b0_sectors = 0, b1_sectors = 0;
- switch (bank->size)
- {
+ switch (bank->size) {
case 16 * 1024:
b1_sectors = 2;
break;
num_sectors = 0;
- for (i = 0; i < b0_sectors; i++)
- {
+ for (i = 0; i < b0_sectors; i++) {
bank->sectors[num_sectors].offset = mem_layout_str7bank0[i].sector_start;
bank->sectors[num_sectors].size = mem_layout_str7bank0[i].sector_size;
bank->sectors[num_sectors].is_erased = -1;
str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank0[i].sector_bit;
}
- for (i = 0; i < b1_sectors; i++)
- {
+ for (i = 0; i < b1_sectors; i++) {
bank->sectors[num_sectors].offset = mem_layout_str7bank1[i].sector_start;
bank->sectors[num_sectors].size = mem_layout_str7bank1[i].sector_size;
bank->sectors[num_sectors].is_erased = -1;
struct str7x_flash_bank *str7x_info;
if (CMD_ARGC < 7)
- {
return ERROR_COMMAND_SYNTAX_ERROR;
- }
str7x_info = malloc(sizeof(struct str7x_flash_bank));
bank->driver_priv = str7x_info;
str7x_info->disable_bit = (1 << 1);
if (strcmp(CMD_ARGV[6], "STR71x") == 0)
- {
str7x_info->register_base = 0x40100000;
- }
- else if (strcmp(CMD_ARGV[6], "STR73x") == 0)
- {
+ else if (strcmp(CMD_ARGV[6], "STR73x") == 0) {
str7x_info->register_base = 0x80100000;
str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA0);
- }
- else if (strcmp(CMD_ARGV[6], "STR75x") == 0)
- {
+ } else if (strcmp(CMD_ARGV[6], "STR75x") == 0) {
str7x_info->register_base = 0x20100000;
str7x_info->disable_bit = (1 << 0);
- }
- else
- {
+ } else {
LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV[6]);
free(str7x_info);
return ERROR_FLASH_BANK_INVALID;
str7x_build_block_list(bank);
- str7x_info->write_algorithm = NULL;
-
return ERROR_OK;
}
struct target *target = bank->target;
struct str7x_flash_bank *str7x_info = bank->driver_priv;
- for (i = 0 ; i < 10000; i++)
- {
+ for (i = 0 ; i < 10000; i++) {
uint32_t retval;
err = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
if (err != ERROR_OK)
if (retval != ERROR_OK)
return retval;
- if (flash_flags & FLASH_WPF)
- {
+ if (flash_flags & FLASH_WPF) {
LOG_ERROR("str7x hw write protection set");
retval = ERROR_FAIL;
}
- if (flash_flags & FLASH_RESER)
- {
+ if (flash_flags & FLASH_RESER) {
LOG_ERROR("str7x suspended program erase not resumed");
retval = ERROR_FAIL;
}
- if (flash_flags & FLASH_10ER)
- {
+ if (flash_flags & FLASH_10ER) {
LOG_ERROR("str7x trying to set bit to 1 when it is already 0");
retval = ERROR_FAIL;
}
- if (flash_flags & FLASH_PGER)
- {
+ if (flash_flags & FLASH_PGER) {
LOG_ERROR("str7x program error");
retval = ERROR_FAIL;
}
- if (flash_flags & FLASH_ERER)
- {
+ if (flash_flags & FLASH_ERER) {
LOG_ERROR("str7x erase error");
retval = ERROR_FAIL;
}
- if (retval == ERROR_OK)
- {
- if (flash_flags & FLASH_ERR)
- {
+ if (retval == ERROR_OK) {
+ if (flash_flags & FLASH_ERR) {
/* this should always be set if one of the others are set... */
LOG_ERROR("str7x write operation failed / bad setup");
retval = ERROR_FAIL;
int i;
uint32_t flash_flags;
- if (bank->target->state != TARGET_HALTED)
- {
+ if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (retval != ERROR_OK)
return retval;
- for (i = 0; i < bank->num_sectors; i++)
- {
+ for (i = 0; i < bank->num_sectors; i++) {
if (flash_flags & str7x_info->sector_bits[i])
bank->sectors[i].is_protected = 0;
else
uint32_t sectors = 0;
int err;
- if (bank->target->state != TARGET_HALTED)
- {
+ if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
for (i = first; i <= last; i++)
- {
sectors |= str7x_info->sector_bits[i];
- }
LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
uint32_t cmd;
uint32_t protect_blocks;
- if (bank->target->state != TARGET_HALTED)
- {
+ if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
protect_blocks = 0xFFFFFFFF;
- if (set)
- {
+ if (set) {
for (i = first; i <= last; i++)
protect_blocks &= ~(str7x_info->sector_bits[i]);
}
return ERROR_OK;
}
-static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer,
+static int str7x_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct str7x_flash_bank *str7x_info = bank->driver_priv;
struct target *target = bank->target;
uint32_t buffer_size = 32768;
+ struct working_area *write_algorithm;
struct working_area *source;
uint32_t address = bank->base + offset;
struct reg_param reg_params[6];
- struct arm_algorithm armv4_5_info;
+ struct arm_algorithm arm_algo;
int retval = ERROR_OK;
/* see contib/loaders/flash/str7x.s for src */
0xe582400c, /* str r4, [r2, #0xc] */
0xe3a04209, /* mov r4, #0x90000000 */
0xe5824000, /* str r4, [r2, #0x0] */
- /* busy: */
+ /* busy: */
0xe5924000, /* ldr r4, [r2, #0x0] */
0xe1140005, /* tst r4, r5 */
0x1afffffc, /* bne busy */
/* flash write code */
if (target_alloc_working_area_try(target, sizeof(str7x_flash_write_code),
- &str7x_info->write_algorithm) != ERROR_OK)
- {
+ &write_algorithm) != ERROR_OK) {
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- };
+ }
- target_write_buffer(target, str7x_info->write_algorithm->address,
- sizeof(str7x_flash_write_code),
- (uint8_t*)str7x_flash_write_code);
+ uint8_t code[sizeof(str7x_flash_write_code)];
+ target_buffer_set_u32_array(target, code, ARRAY_SIZE(str7x_flash_write_code),
+ str7x_flash_write_code);
+ target_write_buffer(target, write_algorithm->address, sizeof(code), code);
/* memory buffer */
- while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
- {
+ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
buffer_size /= 2;
- if (buffer_size <= 256)
- {
- /* if we already allocated the writing code, but failed to get a
+ if (buffer_size <= 256) {
+ /* we already allocated the writing code, but failed to get a
* buffer, free the algorithm */
- if (str7x_info->write_algorithm)
- target_free_working_area(target, str7x_info->write_algorithm);
+ target_free_working_area(target, write_algorithm);
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
}
- armv4_5_info.common_magic = ARM_COMMON_MAGIC;
- armv4_5_info.core_mode = ARM_MODE_SVC;
- armv4_5_info.core_state = ARM_STATE_ARM;
+ arm_algo.common_magic = ARM_COMMON_MAGIC;
+ arm_algo.core_mode = ARM_MODE_SVC;
+ arm_algo.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
init_reg_param(®_params[4], "r4", 32, PARAM_IN);
init_reg_param(®_params[5], "r5", 32, PARAM_OUT);
- while (count > 0)
- {
+ while (count > 0) {
uint32_t thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
target_write_buffer(target, source->address, thisrun_count * 8, buffer);
buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
- if ((retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
- str7x_info->write_algorithm->address,
- str7x_info->write_algorithm->address + (sizeof(str7x_flash_write_code) - 4),
- 10000, &armv4_5_info)) != ERROR_OK)
- {
+ retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
+ write_algorithm->address,
+ write_algorithm->address + (sizeof(str7x_flash_write_code) - 4),
+ 10000, &arm_algo);
+ if (retval != ERROR_OK)
break;
- }
- if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00)
- {
+ if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00) {
retval = str7x_result(bank);
break;
}
}
target_free_working_area(target, source);
- target_free_working_area(target, str7x_info->write_algorithm);
+ target_free_working_area(target, write_algorithm);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
return retval;
}
-static int str7x_write(struct flash_bank *bank, uint8_t *buffer,
+static int str7x_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
uint32_t check_address = offset;
int i;
- if (bank->target->state != TARGET_HALTED)
- {
+ if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- if (offset & 0x7)
- {
+ if (offset & 0x7) {
LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment", offset);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
- for (i = 0; i < bank->num_sectors; i++)
- {
+ for (i = 0; i < bank->num_sectors; i++) {
uint32_t sec_start = bank->sectors[i].offset;
uint32_t sec_end = sec_start + bank->sectors[i].size;
/* check if destination falls within the current sector */
- if ((check_address >= sec_start) && (check_address < sec_end))
- {
+ if ((check_address >= sec_start) && (check_address < sec_end)) {
/* check if destination ends in the current sector */
if (offset + count < sec_end)
check_address = offset + count;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
/* multiple dwords (8-byte) to be programmed? */
- if (dwords_remaining > 0)
- {
+ if (dwords_remaining > 0) {
/* try using a block write */
- if ((retval = str7x_write_block(bank, buffer, offset,
- dwords_remaining)) != ERROR_OK)
- {
- if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
- {
+ retval = str7x_write_block(bank, buffer, offset, dwords_remaining);
+ if (retval != ERROR_OK) {
+ if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
/* if block write failed (no sufficient working area),
* we use normal (slow) single dword accesses */
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
- } else
- {
+ } else {
return retval;
}
- }
- else
- {
+ } else {
buffer += dwords_remaining * 8;
address += dwords_remaining * 8;
dwords_remaining = 0;
}
}
- while (dwords_remaining > 0)
- {
+ while (dwords_remaining > 0) {
/* command */
cmd = FLASH_DWPG;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
address += 8;
}
- if (bytes_remaining)
- {
+ if (bytes_remaining) {
uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
/* copy the last remaining bytes into the write buffer */
static int get_str7x_info(struct flash_bank *bank, char *buf, int buf_size)
{
- snprintf(buf, buf_size, "str7x flash driver info");
- /* STR7x flash doesn't support sector protection interrogation.
- * FLASH_NVWPAR acts as a write only register; its read value
- * doesn't reflect the actual protection state of the sectors.
+ /* Setting the write protection on a sector is a permanent change but it
+ * can be disabled temporarily. FLASH_NVWPAR reflects the permanent
+ * protection state of the sectors, not the temporary.
*/
- LOG_WARNING("STR7x flash lock information might not be correct "
- "due to hardware limitations.");
+ snprintf(buf, buf_size, "STR7x flash protection info is only valid after a power cycle, "
+ "clearing the protection is only temporary and may not be reflected in the current "
+ "info returned.");
return ERROR_OK;
}
uint16_t ProtectionRegs;
if (CMD_ARGC < 1)
- {
return ERROR_COMMAND_SYNTAX_ERROR;
- }
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
target = bank->target;
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), ®);
if (!(reg & str7x_info->disable_bit))
- {
ProtectionLevel = 1;
- }
target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), ®);
ProtectionRegs = ~(reg >> 16);
- while (((ProtectionRegs) != 0) && (ProtectionLevel < 16))
- {
+ while (((ProtectionRegs) != 0) && (ProtectionLevel < 16)) {
ProtectionRegs >>= 1;
ProtectionLevel++;
}
- if (ProtectionLevel == 0)
- {
+ if (ProtectionLevel == 0) {
flash_cmd = FLASH_SPR;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), 0xFFFFFFFD);
flash_cmd = FLASH_SPR | FLASH_WMS;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
- }
- else
- {
+ } else {
flash_cmd = FLASH_SPR;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
COMMAND_REGISTRATION_DONE
};
-struct flash_driver str7x_flash = {
+const struct flash_driver str7x_flash = {
.name = "str7x",
.commands = str7x_command_handlers,
.flash_bank_command = str7x_flash_bank_command,
.erase_check = default_flash_blank_check,
.protect_check = str7x_protect_check,
.info = get_str7x_info,
+ .free_driver_priv = default_flash_free_driver_priv,
};
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