#include "binarybuffer.h"
-#define DID0_VER(did0) ((did0>>28)&0x07)
-static int stellaris_register_commands(struct command_context_s *cmd_ctx);
-static int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
-static int stellaris_erase(struct flash_bank_s *bank, int first, int last);
-static int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int stellaris_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count);
-static int stellaris_auto_probe(struct flash_bank_s *bank);
-static int stellaris_probe(struct flash_bank_s *bank);
-static int stellaris_protect_check(struct flash_bank_s *bank);
-static int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size);
+#define DID0_VER(did0) ((did0 >> 28)&0x07)
static int stellaris_read_part_info(struct flash_bank_s *bank);
static uint32_t stellaris_get_flash_status(flash_bank_t *bank);
static void stellaris_set_flash_mode(flash_bank_t *bank,int mode);
//static uint32_t stellaris_wait_status_busy(flash_bank_t *bank, uint32_t waitbits, int timeout);
-static int stellaris_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
static int stellaris_mass_erase(struct flash_bank_s *bank);
-flash_driver_t stellaris_flash =
-{
- .name = "stellaris",
- .register_commands = stellaris_register_commands,
- .flash_bank_command = stellaris_flash_bank_command,
- .erase = stellaris_erase,
- .protect = stellaris_protect,
- .write = stellaris_write,
- .probe = stellaris_probe,
- .auto_probe = stellaris_auto_probe,
- .erase_check = default_flash_mem_blank_check,
- .protect_check = stellaris_protect_check,
- .info = stellaris_info
-};
-
static struct {
uint32_t partno;
char *partname;
/* flash_bank stellaris <base> <size> 0 0 <target#>
*/
-static int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
+FLASH_BANK_COMMAND_HANDLER(stellaris_flash_bank_command)
{
- stellaris_flash_bank_t *stellaris_info;
+ struct stellaris_flash_bank *stellaris_info;
if (argc < 6)
{
return ERROR_FLASH_BANK_INVALID;
}
- stellaris_info = calloc(sizeof(stellaris_flash_bank_t), 1);
+ stellaris_info = calloc(sizeof(struct stellaris_flash_bank), 1);
bank->base = 0x0;
bank->driver_priv = stellaris_info;
/* part wasn't probed for info yet */
stellaris_info->did1 = 0;
- /* TODO Use an optional main oscillator clock rate in kHz from arg[6] */
- return ERROR_OK;
-}
-
-static int stellaris_register_commands(struct command_context_s *cmd_ctx)
-{
- command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stellaris", NULL, COMMAND_ANY, "stellaris flash specific commands");
-
- register_command(cmd_ctx, stm32x_cmd, "mass_erase", stellaris_handle_mass_erase_command, COMMAND_EXEC, "mass erase device");
+ /* TODO Specify the main crystal speed in kHz using an optional
+ * argument; ditto, the speed of an external oscillator used
+ * instead of a crystal. Avoid programming flash using IOSC.
+ */
return ERROR_OK;
}
static int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
int printed, device_class;
- stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
+ struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
stellaris_read_part_info(bank);
if (DID0_VER(stellaris_info->did0) > 0)
{
- device_class = (stellaris_info->did0>>16) & 0xFF;
+ device_class = (stellaris_info->did0 >> 16) & 0xFF;
}
else
{
device_class = 0;
}
- printed = snprintf(buf,
+ printed = snprintf(buf,
buf_size,
- "\nLMI Stellaris information: Chip is class %i(%s) %s v%c.%i\n",
- device_class,
- StellarisClassname[device_class],
+ "\nTI/LMI Stellaris information: Chip is "
+ "class %i (%s) %s rev %c%i\n",
+ device_class,
+ StellarisClassname[device_class],
stellaris_info->target_name,
- (int)('A' + ((stellaris_info->did0>>8) & 0xFF)),
+ (int)('A' + ((stellaris_info->did0 >> 8) & 0xFF)),
(int)((stellaris_info->did0) & 0xFF));
buf += printed;
buf_size -= printed;
- printed = snprintf(buf,
- buf_size,
- "did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32 ", eproc: %s, ramsize:%ik, flashsize: %ik\n",
- stellaris_info->did1,
- stellaris_info->did1,
- "ARMV7M",
- (int)((1+((stellaris_info->dc0>>16) & 0xFFFF))/4),
- (int)((1+(stellaris_info->dc0 & 0xFFFF))*2));
+ printed = snprintf(buf,
+ buf_size,
+ "did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32
+ ", eproc: %s, ramsize: %ik, flashsize: %ik\n",
+ stellaris_info->did1,
+ stellaris_info->did1,
+ "ARMv7M",
+ (int)((1 + ((stellaris_info->dc0 >> 16) & 0xFFFF))/4),
+ (int)((1 + (stellaris_info->dc0 & 0xFFFF))*2));
buf += printed;
buf_size -= printed;
- printed = snprintf(buf,
+ printed = snprintf(buf,
buf_size,
- "master clock(estimated): %ikHz, rcc is 0x%" PRIx32 " \n",
- (int)(stellaris_info->mck_freq / 1000),
- stellaris_info->rcc);
+ "master clock: %ikHz%s, "
+ "rcc is 0x%" PRIx32 ", rcc2 is 0x%" PRIx32 "\n",
+ (int)(stellaris_info->mck_freq / 1000),
+ stellaris_info->mck_desc,
+ stellaris_info->rcc,
+ stellaris_info->rcc2);
buf += printed;
buf_size -= printed;
- if (stellaris_info->num_lockbits>0)
+ if (stellaris_info->num_lockbits > 0)
{
printed = snprintf(buf,
buf_size,
- "pagesize: %" PRIi32 ", lockbits: %i 0x%4.4" PRIx32 ", pages in lock region: %i \n",
- stellaris_info->pagesize,
- stellaris_info->num_lockbits,
+ "pagesize: %" PRIi32 ", lockbits: %i 0x%4.4" PRIx32 ", pages in lock region: %i \n",
+ stellaris_info->pagesize,
+ stellaris_info->num_lockbits,
stellaris_info->lockbits,
(int)(stellaris_info->num_pages/stellaris_info->num_lockbits));
buf += printed;
static uint32_t stellaris_get_flash_status(flash_bank_t *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t fmc;
- target_read_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, &fmc);
+ target_read_u32(target, FLASH_CONTROL_BASE | FLASH_FMC, &fmc);
return fmc;
}
/** Read clock configuration and set stellaris_info->usec_clocks*/
+static const unsigned rcc_xtal[32] = {
+ [0x00] = 1000000, /* no pll */
+ [0x01] = 1843200, /* no pll */
+ [0x02] = 2000000, /* no pll */
+ [0x03] = 2457600, /* no pll */
+
+ [0x04] = 3579545,
+ [0x05] = 3686400,
+ [0x06] = 4000000, /* usb */
+ [0x07] = 4096000,
+
+ [0x08] = 4915200,
+ [0x09] = 5000000, /* usb */
+ [0x0a] = 5120000,
+ [0x0b] = 6000000, /* (reset) usb */
+
+ [0x0c] = 6144000,
+ [0x0d] = 7372800,
+ [0x0e] = 8000000, /* usb */
+ [0x0f] = 8192000,
+
+ /* parts before DustDevil use just 4 bits for xtal spec */
+
+ [0x10] = 10000000, /* usb */
+ [0x11] = 12000000, /* usb */
+ [0x12] = 12288000,
+ [0x13] = 13560000,
+
+ [0x14] = 14318180,
+ [0x15] = 16000000, /* usb */
+ [0x16] = 16384000,
+};
+
static void stellaris_read_clock_info(flash_bank_t *bank)
{
- stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
- target_t *target = bank->target;
- uint32_t rcc, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
+ struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
+ struct target *target = bank->target;
+ uint32_t rcc, rcc2, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
+ unsigned xtal;
unsigned long mainfreq;
- target_read_u32(target, SCB_BASE|RCC, &rcc);
+ target_read_u32(target, SCB_BASE | RCC, &rcc);
LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
- target_read_u32(target, SCB_BASE|PLLCFG, &pllcfg);
+
+ target_read_u32(target, SCB_BASE | RCC2, &rcc2);
+ LOG_DEBUG("Stellaris RCC2 %" PRIx32 "", rcc);
+
+ target_read_u32(target, SCB_BASE | PLLCFG, &pllcfg);
LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
+
stellaris_info->rcc = rcc;
+ stellaris_info->rcc = rcc2;
+
+ sysdiv = (rcc >> 23) & 0xF;
+ usesysdiv = (rcc >> 22) & 0x1;
+ bypass = (rcc >> 11) & 0x1;
+ oscsrc = (rcc >> 4) & 0x3;
+ xtal = (rcc >> 6) & stellaris_info->xtal_mask;
+
+ /* NOTE: post-Sandstorm parts have RCC2 which may override
+ * parts of RCC ... with more sysdiv options, option for
+ * 32768 Hz mainfreq, PLL controls. On Sandstorm it reads
+ * as zero, so the "use RCC2" flag is always clear.
+ */
+ if (rcc2 & (1 << 31)) {
+ sysdiv = (rcc2 >> 23) & 0x3F;
+ bypass = (rcc2 >> 11) & 0x1;
+ oscsrc = (rcc2 >> 4) & 0x7;
+
+ /* FIXME Tempest parts have an additional lsb for
+ * fractional sysdiv (200 MHz / 2.5 == 80 MHz)
+ */
+ }
+
+ stellaris_info->mck_desc = "";
- sysdiv = (rcc>>23) & 0xF;
- usesysdiv = (rcc>>22) & 0x1;
- bypass = (rcc>>11) & 0x1;
- oscsrc = (rcc>>4) & 0x3;
- /* xtal = (rcc>>6)&0xF; */
switch (oscsrc)
{
- case 0:
- mainfreq = 6000000; /* Default xtal */
+ case 0: /* MOSC */
+ mainfreq = rcc_xtal[xtal];
+ break;
+ case 1: /* IOSC */
+ mainfreq = stellaris_info->iosc_freq;
+ stellaris_info->mck_desc = stellaris_info->iosc_desc;
break;
- case 1:
- mainfreq = 22500000; /* Internal osc. 15 MHz +- 50% */
+ case 2: /* IOSC/4 */
+ mainfreq = stellaris_info->iosc_freq / 4;
+ stellaris_info->mck_desc = stellaris_info->iosc_desc;
break;
- case 2:
- mainfreq = 5625000; /* Internal osc. / 4 */
+ case 3: /* lowspeed */
+ /* Sandstorm doesn't have this 30K +/- 30% osc */
+ mainfreq = 30000;
+ stellaris_info->mck_desc = " (±30%)";
break;
- case 3:
- LOG_WARNING("Invalid oscsrc (3) in rcc register");
- mainfreq = 6000000;
+ case 8: /* hibernation osc */
+ /* not all parts support hibernation */
+ mainfreq = 32768;
break;
default: /* NOTREACHED */
break;
}
+ /* PLL is used if it's not bypassed; its output is 200 MHz
+ * even when it runs at 400 MHz (adds divide-by-two stage).
+ */
if (!bypass)
- mainfreq = 200000000; /* PLL out frec */
+ mainfreq = 200000000;
if (usesysdiv)
- stellaris_info->mck_freq = mainfreq/(1+sysdiv);
+ stellaris_info->mck_freq = mainfreq/(1 + sysdiv);
else
stellaris_info->mck_freq = mainfreq;
/* Setup the timimg registers */
static void stellaris_set_flash_mode(flash_bank_t *bank,int mode)
{
- stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
+ struct target *target = bank->target;
uint32_t usecrl = (stellaris_info->mck_freq/1000000ul-1);
LOG_DEBUG("usecrl = %i",(int)(usecrl));
- target_write_u32(target, SCB_BASE|USECRL, usecrl);
+ target_write_u32(target, SCB_BASE | USECRL, usecrl);
}
#if 0
static int stellaris_flash_command(struct flash_bank_s *bank,uint8_t cmd,uint16_t pagen)
{
uint32_t fmc;
- target_t *target = bank->target;
+ struct target *target = bank->target;
fmc = FMC_WRKEY | cmd;
- target_write_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, fmc);
+ target_write_u32(target, FLASH_CONTROL_BASE | FLASH_FMC, fmc);
LOG_DEBUG("Flash command: 0x%x", fmc);
if (stellaris_wait_status_busy(bank, cmd, 100))
/* Read device id register, main clock frequency register and fill in driver info structure */
static int stellaris_read_part_info(struct flash_bank_s *bank)
{
- stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
+ struct target *target = bank->target;
uint32_t did0, did1, ver, fam, status;
int i;
/* Read and parse chip identification register */
- target_read_u32(target, SCB_BASE|DID0, &did0);
- target_read_u32(target, SCB_BASE|DID1, &did1);
- target_read_u32(target, SCB_BASE|DC0, &stellaris_info->dc0);
- target_read_u32(target, SCB_BASE|DC1, &stellaris_info->dc1);
+ target_read_u32(target, SCB_BASE | DID0, &did0);
+ target_read_u32(target, SCB_BASE | DID1, &did1);
+ target_read_u32(target, SCB_BASE | DC0, &stellaris_info->dc0);
+ target_read_u32(target, SCB_BASE | DC1, &stellaris_info->dc1);
LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32 "",
did0, did1, stellaris_info->dc0, stellaris_info->dc1);
LOG_WARNING("Unknown did1 version/family, cannot positively identify target as a Stellaris");
}
+ /* For Sandstorm, Fury, DustDevil: current data sheets say IOSC
+ * is 12 MHz, but some older parts have 15 MHz. A few data sheets
+ * even give _both_ numbers! We'll use current numbers; IOSC is
+ * always approximate.
+ *
+ * For Tempest: IOSC is calibrated, 16 MHz
+ */
+ stellaris_info->iosc_freq = 12000000;
+ stellaris_info->iosc_desc = " (±30%)";
+ stellaris_info->xtal_mask = 0x0f;
+
+ switch ((did0 >> 28) & 0x7) {
+ case 0: /* Sandstorm */
+ /*
+ * Current (2009-August) parts seem to be rev C2 and use 12 MHz.
+ * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
+ * (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
+ */
+ if (((did0 >> 8) & 0xff) < 2) {
+ stellaris_info->iosc_freq = 15000000;
+ stellaris_info->iosc_desc = " (±50%)";
+ }
+ break;
+ case 1:
+ switch ((did0 >> 16) & 0xff) {
+ case 1: /* Fury */
+ break;
+ case 4: /* Tempest */
+ stellaris_info->iosc_freq = 16000000; /* +/- 1% */
+ stellaris_info->iosc_desc = " (±1%)";
+ /* FALL THROUGH */
+ case 3: /* DustDevil */
+ stellaris_info->xtal_mask = 0x1f;
+ break;
+ default:
+ LOG_WARNING("Unknown did0 class");
+ }
+ default:
+ break;
+ LOG_WARNING("Unknown did0 version");
+ }
+
for (i = 0; StellarisParts[i].partno; i++)
{
if (StellarisParts[i].partno == ((did1 >> 16) & 0xFF))
stellaris_info->did1 = did1;
stellaris_info->num_lockbits = 1 + (stellaris_info->dc0 & 0xFFFF);
- stellaris_info->num_pages = 2 *(1+(stellaris_info->dc0 & 0xFFFF));
+ stellaris_info->num_pages = 2 *(1 + (stellaris_info->dc0 & 0xFFFF));
stellaris_info->pagesize = 1024;
bank->size = 1024 * stellaris_info->num_pages;
stellaris_info->pages_in_lockregion = 2;
- target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits);
+ target_read_u32(target, SCB_BASE | FMPPE, &stellaris_info->lockbits);
/* provide this for the benefit of the higher flash driver layers */
bank->num_sectors = stellaris_info->num_pages;
- bank->sectors = malloc(sizeof(flash_sector_t) * bank->num_sectors);
+ bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
for (i = 0; i < bank->num_sectors; i++)
{
bank->sectors[i].offset = i * stellaris_info->pagesize;
{
uint32_t status;
- stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
+ struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
if (bank->target->state != TARGET_HALTED)
{
if (stellaris_info->did1 == 0)
{
- LOG_WARNING("Cannot identify target as an AT91SAM");
+ LOG_WARNING("Cannot identify target as Stellaris");
return ERROR_FLASH_OPERATION_FAILED;
}
{
int banknr;
uint32_t flash_fmc, flash_cris;
- stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
+ struct target *target = bank->target;
if (bank->target->state != TARGET_HALTED)
{
/* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0);
- target_write_u32(target, FLASH_MISC, PMISC|AMISC);
+ target_write_u32(target, FLASH_MISC, PMISC | AMISC);
for (banknr = first; banknr <= last; banknr++)
{
uint32_t fmppe, flash_fmc, flash_cris;
int lockregion;
- stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
+ struct target *target = bank->target;
if (bank->target->state != TARGET_HALTED)
{
for (lockregion = first; lockregion <= last; lockregion++)
{
if (set)
- fmppe &= ~(1<<lockregion);
+ fmppe &= ~(1 << lockregion);
else
- fmppe |= (1<<lockregion);
+ fmppe |= (1 << lockregion);
}
/* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0);
- target_write_u32(target, FLASH_MISC, PMISC|AMISC);
+ target_write_u32(target, FLASH_MISC, PMISC | AMISC);
LOG_DEBUG("fmppe 0x%" PRIx32 "",fmppe);
- target_write_u32(target, SCB_BASE|FMPPE, fmppe);
+ target_write_u32(target, SCB_BASE | FMPPE, fmppe);
/* Commit FMPPE */
target_write_u32(target, FLASH_FMA, 1);
/* Write commit command */
return ERROR_FLASH_OPERATION_FAILED;
}
- target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits);
+ target_read_u32(target, SCB_BASE | FMPPE, &stellaris_info->lockbits);
return ERROR_OK;
}
static int stellaris_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t wcount)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t buffer_size = 8192;
- working_area_t *source;
- working_area_t *write_algorithm;
+ struct working_area *source;
+ struct working_area *write_algorithm;
uint32_t address = bank->base + offset;
- reg_param_t reg_params[3];
- armv7m_algorithm_t armv7m_info;
+ struct reg_param reg_params[3];
+ struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, address);
buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
- LOG_INFO("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, wcount);
- LOG_DEBUG("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, wcount);
+ LOG_INFO("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, (wcount - thisrun_count));
+ LOG_DEBUG("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, (wcount - thisrun_count));
if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params, write_algorithm->address, write_algorithm->address + sizeof(stellaris_write_code)-10, 10000, &armv7m_info)) != ERROR_OK)
{
LOG_ERROR("error executing stellaris flash write algorithm");
static int stellaris_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
- stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
+ struct target *target = bank->target;
uint32_t address = offset;
uint32_t flash_cris, flash_fmc;
uint32_t words_remaining = (count / 4);
/* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0);
- target_write_u32(target, FLASH_MISC, PMISC|AMISC);
+ target_write_u32(target, FLASH_MISC, PMISC | AMISC);
/* multiple words to be programmed? */
if (words_remaining > 0)
static int stellaris_auto_probe(struct flash_bank_s *bank)
{
- stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
+ struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
if (stellaris_info->did1)
return ERROR_OK;
return stellaris_probe(bank);
static int stellaris_mass_erase(struct flash_bank_s *bank)
{
- target_t *target = NULL;
- stellaris_flash_bank_t *stellaris_info = NULL;
+ struct target *target = NULL;
+ struct stellaris_flash_bank *stellaris_info = NULL;
uint32_t flash_fmc;
stellaris_info = bank->driver_priv;
/* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0);
- target_write_u32(target, FLASH_MISC, PMISC|AMISC);
+ target_write_u32(target, FLASH_MISC, PMISC | AMISC);
target_write_u32(target, FLASH_FMA, 0);
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
return ERROR_OK;
}
-static int stellaris_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(stellaris_handle_mass_erase_command)
{
- flash_bank_t *bank;
int i;
if (argc < 1)
return ERROR_OK;
}
- bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
- if (!bank)
- {
- command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
- return ERROR_OK;
- }
+ flash_bank_t *bank;
+ int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
+ if (ERROR_OK != retval)
+ return retval;
if (stellaris_mass_erase(bank) == ERROR_OK)
{
return ERROR_OK;
}
+
+static int stellaris_register_commands(struct command_context_s *cmd_ctx)
+{
+ command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stellaris",
+ NULL, COMMAND_ANY, "stellaris flash specific commands");
+
+ register_command(cmd_ctx, stm32x_cmd, "mass_erase",
+ stellaris_handle_mass_erase_command, COMMAND_EXEC,
+ "mass erase device");
+ return ERROR_OK;
+}
+
+
+struct flash_driver stellaris_flash = {
+ .name = "stellaris",
+ .register_commands = &stellaris_register_commands,
+ .flash_bank_command = &stellaris_flash_bank_command,
+ .erase = &stellaris_erase,
+ .protect = &stellaris_protect,
+ .write = &stellaris_write,
+ .probe = &stellaris_probe,
+ .auto_probe = &stellaris_auto_probe,
+ .erase_check = &default_flash_mem_blank_check,
+ .protect_check = &stellaris_protect_check,
+ .info = &stellaris_info,
+ };
Code Review / openocd.git / blobdiff