+ /* There are multiple revisions of LM3S811 eval boards:
+ * - Rev B (and older?) boards have no SWO trace support.
+ * - Rev C boards add ADBUS_6 DBG_ENn and BDBUS_4 SWO_EN;
+ * they should use the "luminary_icdi" layout instead.
+ */
+ nTRST = 0x0;
+ nTRSTnOE = 0x00;
+ nSRST = 0x20;
+ nSRSTnOE = 0x20;
+ low_output = 0x88;
+ low_direction = 0x8b;
+
+ return ftx232_dbus_write();
+}
+
+static int icdi_jtag_init(void)
+{
+ ftx232_dbus_init();
+
+ /* Most Luminary eval boards support SWO trace output,
+ * and should use this "luminary_icdi" layout.
+ *
+ * ADBUS 0..3 are used for JTAG as usual. GPIOs are used
+ * to switch between JTAG and SWD, or switch the ft2232 UART
+ * on the second MPSSE channel/interface (BDBUS)
+ * between (i) the stellaris UART (on Luminary boards)
+ * or (ii) SWO trace data (generic).
+ *
+ * We come up in JTAG mode and may switch to SWD later (with
+ * SWO/trace option if SWD is active).
+ *
+ * DBUS == GPIO-Lx
+ * CBUS == GPIO-Hx
+ */
+
+
+#define ICDI_JTAG_EN (1 << 7) /* ADBUS 7 (a.k.a. DBGMOD) */
+#define ICDI_DBG_ENn (1 << 6) /* ADBUS 6 */
+#define ICDI_SRST (1 << 5) /* ADBUS 5 */
+
+
+ /* GPIOs on second channel/interface (UART) ... */
+#define ICDI_SWO_EN (1 << 4) /* BDBUS 4 */
+#define ICDI_TX_SWO (1 << 1) /* BDBUS 1 */
+#define ICDI_VCP_RX (1 << 0) /* BDBUS 0 (to stellaris UART) */
+
+ nTRST = 0x0;
+ nTRSTnOE = 0x00;
+ nSRST = ICDI_SRST;
+ nSRSTnOE = ICDI_SRST;
+
+ low_direction |= ICDI_JTAG_EN | ICDI_DBG_ENn;
+ low_output |= ICDI_JTAG_EN;
+ low_output &= ~ICDI_DBG_ENn;
+
+ return ftx232_dbus_write();
+}
+
+static int signalyzer_init(void)
+{
+ ftx232_dbus_init();
+
+ nTRST = 0x10;
+ nTRSTnOE = 0x10;
+ nSRST = 0x20;
+ nSRSTnOE = 0x20;
+ return ftx232_dbus_write();
+}
+
+static int axm0432_jtag_init(void)
+{