adiv6: re-organize mem_ap registers definition

[openocd.git] / src / jtag / drivers / rshim.c

diff --git a/src/jtag/drivers/rshim.c b/src/jtag/drivers/rshim.c
index 246e931c22fed04bfc1a8231a7e73b2ecd3a93b7..881b23f19bd4cf2b6bfd9a475eedc061998380c7 100644 (file)
--- a/src/jtag/drivers/rshim.c
+++ b/src/jtag/drivers/rshim.c
@@ -283,35 +283,35 @@ static int rshim_ap_q_read(struct adiv5_ap *ap, unsigned int reg,
        int rc = ERROR_OK, tile;
 
        switch (reg) {
-       case MEM_AP_REG_CSW:
+       case ADIV5_MEM_AP_REG_CSW:
                *data = ap_csw;
                break;
 
-       case MEM_AP_REG_CFG:
+       case ADIV5_MEM_AP_REG_CFG:
                *data = 0;
                break;
 
-       case MEM_AP_REG_BASE:
+       case ADIV5_MEM_AP_REG_BASE:
                *data = RSH_CS_ROM_BASE;
                break;
 
-       case AP_REG_IDR:
+       case ADIV5_AP_REG_IDR:
                if (ap->ap_num == 0)
                        *data = APB_AP_IDR;
                else
                        *data = 0;
                break;
 
-       case MEM_AP_REG_BD0:
-       case MEM_AP_REG_BD1:
-       case MEM_AP_REG_BD2:
-       case MEM_AP_REG_BD3:
+       case ADIV5_MEM_AP_REG_BD0:
+       case ADIV5_MEM_AP_REG_BD1:
+       case ADIV5_MEM_AP_REG_BD2:
+       case ADIV5_MEM_AP_REG_BD3:
                addr = (ap_tar & ~0xf) + (reg & 0x0C);
                ap_addr_2_tile(&tile, &addr);
                rc = coresight_read(tile, addr, data);
                break;
 
-       case MEM_AP_REG_DRW:
+       case ADIV5_MEM_AP_REG_DRW:
                addr = (ap_tar & ~0x3) + ap_tar_inc;
                ap_addr_2_tile(&tile, &addr);
                rc = coresight_read(tile, addr, data);
@@ -344,25 +344,25 @@ static int rshim_ap_q_write(struct adiv5_ap *ap, unsigned int reg,
        }
 
        switch (reg) {
-       case MEM_AP_REG_CSW:
+       case ADIV5_MEM_AP_REG_CSW:
                ap_csw = data;
                break;
 
-       case MEM_AP_REG_TAR:
+       case ADIV5_MEM_AP_REG_TAR:
                ap_tar = data;
                ap_tar_inc = 0;
                break;
 
-       case MEM_AP_REG_BD0:
-       case MEM_AP_REG_BD1:
-       case MEM_AP_REG_BD2:
-       case MEM_AP_REG_BD3:
+       case ADIV5_MEM_AP_REG_BD0:
+       case ADIV5_MEM_AP_REG_BD1:
+       case ADIV5_MEM_AP_REG_BD2:
+       case ADIV5_MEM_AP_REG_BD3:
                addr = (ap_tar & ~0xf) + (reg & 0x0C);
                ap_addr_2_tile(&tile, &addr);
                rc = coresight_write(tile, addr, data);
                break;
 
-       case MEM_AP_REG_DRW:
+       case ADIV5_MEM_AP_REG_DRW:
                ap_drw = data;
                addr = (ap_tar & ~0x3) + ap_tar_inc;
                ap_addr_2_tile(&tile, &addr);