- u8 TDO_MASK; /* status port bit containing current TDO value */
- u8 TRST_MASK; /* data port bit for TRST */
- u8 TMS_MASK; /* data port bit for TMS */
- u8 TCK_MASK; /* data port bit for TCK */
- u8 TDI_MASK; /* data port bit for TDI */
- u8 SRST_MASK; /* data port bit for SRST */
- u8 OUTPUT_INVERT; /* data port bits that should be inverted */
- u8 INPUT_INVERT; /* status port that should be inverted */
- u8 PORT_INIT; /* initialize data port with this value */
-} cable_t;
-
-cable_t cables[] =
-{
- /* name tdo trst tms tck tdi srst o_inv i_inv init */
- { "wiggler", 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x01, 0x80, 0x80 },
- { "old_amt_wiggler", 0x80, 0x01, 0x02, 0x04, 0x08, 0x10, 0x11, 0x80, 0x80 },
- { "chameleon", 0x80, 0x00, 0x04, 0x01, 0x02, 0x00, 0x00, 0x80, 0x00 },
- { "dlc5", 0x10, 0x00, 0x04, 0x02, 0x01, 0x00, 0x00, 0x00, 0x10 },
- { "triton", 0x80, 0x08, 0x04, 0x01, 0x02, 0x00, 0x00, 0x80, 0x00 },
- { "lattice", 0x40, 0x10, 0x04, 0x02, 0x01, 0x08, 0x00, 0x00, 0x18 },
- { "flashlink", 0x20, 0x10, 0x02, 0x01, 0x04, 0x20, 0x30, 0x20, 0x00 },
- { NULL, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+ uint8_t TDO_MASK; /* status port bit containing current TDO value */
+ uint8_t TRST_MASK; /* data port bit for TRST */
+ uint8_t TMS_MASK; /* data port bit for TMS */
+ uint8_t TCK_MASK; /* data port bit for TCK */
+ uint8_t TDI_MASK; /* data port bit for TDI */
+ uint8_t SRST_MASK; /* data port bit for SRST */
+ uint8_t OUTPUT_INVERT; /* data port bits that should be inverted */
+ uint8_t INPUT_INVERT; /* status port that should be inverted */
+ uint8_t PORT_INIT; /* initialize data port with this value */
+ uint8_t PORT_EXIT; /* de-initialize data port with this value */
+ uint8_t LED_MASK; /* data port bit for LED */
+};
+
+static struct cable cables[] =
+{
+ /* name tdo trst tms tck tdi srst o_inv i_inv init exit led */
+ { "wiggler", 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x01, 0x80, 0x80, 0x80, 0x00 },
+ { "wiggler2", 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x01, 0x80, 0x80, 0x00, 0x20 },
+ { "wiggler_ntrst_inverted",
+ 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x11, 0x80, 0x80, 0x80, 0x00 },
+ { "old_amt_wiggler", 0x80, 0x01, 0x02, 0x04, 0x08, 0x10, 0x11, 0x80, 0x80, 0x80, 0x00 },
+ { "arm-jtag", 0x80, 0x01, 0x02, 0x04, 0x08, 0x10, 0x01, 0x80, 0x80, 0x80, 0x00 },
+ { "chameleon", 0x80, 0x00, 0x04, 0x01, 0x02, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00 },
+ { "dlc5", 0x10, 0x00, 0x04, 0x02, 0x01, 0x00, 0x00, 0x00, 0x10, 0x10, 0x00 },
+ { "triton", 0x80, 0x08, 0x04, 0x01, 0x02, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00 },
+ { "lattice", 0x40, 0x10, 0x04, 0x02, 0x01, 0x08, 0x00, 0x00, 0x18, 0x18, 0x00 },
+ { "flashlink", 0x20, 0x10, 0x02, 0x01, 0x04, 0x20, 0x30, 0x20, 0x00, 0x00, 0x00 },
+/* Altium Universal JTAG cable. Set the cable to Xilinx Mode and wire to target as follows:
+ HARD TCK - Target TCK
+ HARD TMS - Target TMS
+ HARD TDI - Target TDI
+ HARD TDO - Target TDO
+ SOFT TCK - Target TRST
+ SOFT TDI - Target SRST
+*/
+ { "altium", 0x10, 0x20, 0x04, 0x02, 0x01, 0x80, 0x00, 0x00, 0x10, 0x00, 0x08 },
+ { NULL, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }