+#define THREADX_NUM_STATES ARRAY_SIZE(threadx_thread_states)
+
+#define ARM926EJS_REGISTERS_SIZE_SOLICITED (11 * 4)
+static const struct stack_register_offset rtos_threadx_arm926ejs_stack_offsets_solicited[] = {
+ { 0, -1, 32 }, /* r0 */
+ { 1, -1, 32 }, /* r1 */
+ { 2, -1, 32 }, /* r2 */
+ { 3, -1, 32 }, /* r3 */
+ { 4, 0x08, 32 }, /* r4 */
+ { 5, 0x0C, 32 }, /* r5 */
+ { 6, 0x10, 32 }, /* r6 */
+ { 7, 0x14, 32 }, /* r7 */
+ { 8, 0x18, 32 }, /* r8 */
+ { 9, 0x1C, 32 }, /* r9 */
+ { 10, 0x20, 32 }, /* r10 */
+ { 11, 0x24, 32 }, /* r11 */
+ { 12, -1, 32 }, /* r12 */
+ { 13, -2, 32 }, /* sp (r13) */
+ { 14, 0x28, 32 }, /* lr (r14) */
+ { 15, -1, 32 }, /* pc (r15) */
+ /*{ 16, -1, 32 },*/ /* lr (r14) */
+ /*{ 17, 0x28, 32 },*/ /* pc (r15) */
+ { 16, 0x04, 32 }, /* xPSR */
+};
+#define ARM926EJS_REGISTERS_SIZE_INTERRUPT (17 * 4)
+static const struct stack_register_offset rtos_threadx_arm926ejs_stack_offsets_interrupt[] = {
+ { 0, 0x08, 32 }, /* r0 */
+ { 1, 0x0C, 32 }, /* r1 */
+ { 2, 0x10, 32 }, /* r2 */
+ { 3, 0x14, 32 }, /* r3 */
+ { 4, 0x18, 32 }, /* r4 */
+ { 5, 0x1C, 32 }, /* r5 */
+ { 6, 0x20, 32 }, /* r6 */
+ { 7, 0x24, 32 }, /* r7 */
+ { 8, 0x28, 32 }, /* r8 */
+ { 9, 0x2C, 32 }, /* r9 */
+ { 10, 0x30, 32 }, /* r10 */
+ { 11, 0x34, 32 }, /* r11 */
+ { 12, 0x38, 32 }, /* r12 */
+ { 13, -2, 32 }, /* sp (r13) */
+ { 14, 0x3C, 32 }, /* lr (r14) */
+ { 15, 0x40, 32 }, /* pc (r15) */
+ { 16, 0x04, 32 }, /* xPSR */
+};
+
+static const struct rtos_register_stacking rtos_threadx_arm926ejs_stacking[] = {
+{
+ .stack_registers_size = ARM926EJS_REGISTERS_SIZE_SOLICITED,
+ .stack_growth_direction = -1,
+ .num_output_registers = 17,
+ .register_offsets = rtos_threadx_arm926ejs_stack_offsets_solicited
+},
+{
+ .stack_registers_size = ARM926EJS_REGISTERS_SIZE_INTERRUPT,
+ .stack_growth_direction = -1,
+ .num_output_registers = 17,
+ .register_offsets = rtos_threadx_arm926ejs_stack_offsets_interrupt
+},
+};