+static struct stack_register_offset rtos_ecos_regoff_arm[] = {
+ { 0, -1, 32 }, /* r0 */
+ { 1, -1, 32 }, /* r1 */
+ { 2, -1, 32 }, /* r2 */
+ { 3, -1, 32 }, /* r3 */
+ { 4, -1, 32 }, /* r4 */
+ { 5, -1, 32 }, /* r5 */
+ { 6, -1, 32 }, /* r6 */
+ { 7, -1, 32 }, /* r7 */
+ { 8, -1, 32 }, /* r8 */
+ { 9, -1, 32 }, /* r9 */
+ { 10, -1, 32 }, /* r10 */
+ { 11, -1, 32 }, /* r11 (fp) */
+ { 12, -1, 32 }, /* r12 (ip) */
+ { 13, -1, 32 }, /* sp (r13) */
+ { 14, -1, 32 }, /* lr (r14) */
+ { 15, -1, 32 }, /* pc (r15) */
+ { 16, -1, 32 }, /* xPSR */
+};
+
+static struct rtos_register_stacking rtos_ecos_stacking = {
+ .stack_registers_size = 0,
+ .stack_growth_direction = -1,
+ .num_output_registers = 0,
+ .calculate_process_stack = NULL, /* stack_alignment */
+ .register_offsets = NULL
+};
+
+/* To avoid the run-time cost of matching explicit symbol names we push the
+ * lookup offsets to this *manually* maintained enumeration which must match the
+ * ecos_symbol_list[] order below. */
+enum ecos_symbol_values {
+ ECOS_VAL_THREAD_LIST = 0,
+ ECOS_VAL_CURRENT_THREAD_PTR,
+ ECOS_VAL_COMMON_THREAD_NEXT_OFF,
+ ECOS_VAL_COMMON_THREAD_NEXT_SIZE,
+ ECOS_VAL_COMMON_THREAD_STATE_OFF,
+ ECOS_VAL_COMMON_THREAD_STATE_SIZE,
+ ECOS_VAL_COMMON_THREAD_SLEEP_OFF,
+ ECOS_VAL_COMMON_THREAD_SLEEP_SIZE,
+ ECOS_VAL_COMMON_THREAD_WAKE_OFF,
+ ECOS_VAL_COMMON_THREAD_WAKE_SIZE,
+ ECOS_VAL_COMMON_THREAD_ID_OFF,
+ ECOS_VAL_COMMON_THREAD_ID_SIZE,
+ ECOS_VAL_COMMON_THREAD_NAME_OFF,
+ ECOS_VAL_COMMON_THREAD_NAME_SIZE,
+ ECOS_VAL_COMMON_THREAD_PRI_OFF,
+ ECOS_VAL_COMMON_THREAD_PRI_SIZE,
+ ECOS_VAL_COMMON_THREAD_STACK_OFF,
+ ECOS_VAL_COMMON_THREAD_STACK_SIZE,
+ ECOS_VAL_CORTEXM_THREAD_SAVED,
+ ECOS_VAL_CORTEXM_CTX_THREAD_SIZE,
+ ECOS_VAL_CORTEXM_CTX_TYPE_OFF,
+ ECOS_VAL_CORTEXM_CTX_TYPE_SIZE,
+ ECOS_VAL_CORTEXM_CTX_BASEPRI_OFF,
+ ECOS_VAL_CORTEXM_CTX_BASEPRI_SIZE,
+ ECOS_VAL_CORTEXM_CTX_SP_OFF,
+ ECOS_VAL_CORTEXM_CTX_SP_SIZE,
+ ECOS_VAL_CORTEXM_CTX_REG_OFF,
+ ECOS_VAL_CORTEXM_CTX_REG_SIZE,
+ ECOS_VAL_CORTEXM_CTX_PC_OFF,
+ ECOS_VAL_CORTEXM_CTX_PC_SIZE,
+ ECOS_VAL_CORTEXM_VAL_EXCEPTION,
+ ECOS_VAL_CORTEXM_VAL_THREAD,
+ ECOS_VAL_CORTEXM_VAL_INTERRUPT,
+ ECOS_VAL_CORTEXM_VAL_FPU,
+ ECOS_VAL_CORTEXM_CTX_FPSCR_OFF,
+ ECOS_VAL_CORTEXM_CTX_FPSCR_SIZE,
+ ECOS_VAL_CORTEXM_CTX_S_OFF,
+ ECOS_VAL_CORTEXM_CTX_S_SIZE,
+ ECOS_VAL_ARM_REGSIZE,
+ ECOS_VAL_ARM_CTX_R0_OFF,
+ ECOS_VAL_ARM_CTX_R1_OFF,
+ ECOS_VAL_ARM_CTX_R2_OFF,
+ ECOS_VAL_ARM_CTX_R3_OFF,
+ ECOS_VAL_ARM_CTX_R4_OFF,
+ ECOS_VAL_ARM_CTX_R5_OFF,
+ ECOS_VAL_ARM_CTX_R6_OFF,
+ ECOS_VAL_ARM_CTX_R7_OFF,
+ ECOS_VAL_ARM_CTX_R8_OFF,
+ ECOS_VAL_ARM_CTX_R9_OFF,
+ ECOS_VAL_ARM_CTX_R10_OFF,
+ ECOS_VAL_ARM_CTX_FP_OFF,
+ ECOS_VAL_ARM_CTX_IP_OFF,
+ ECOS_VAL_ARM_CTX_SP_OFF,
+ ECOS_VAL_ARM_CTX_LR_OFF,
+ ECOS_VAL_ARM_CTX_PC_OFF,
+ ECOS_VAL_ARM_CTX_CPSR_OFF,
+ ECOS_VAL_ARM_FPUSIZE,
+ ECOS_VAL_ARM_CTX_FPSCR_OFF,
+ ECOS_VAL_ARM_SCOUNT,
+ ECOS_VAL_ARM_CTX_SVEC_OFF,
+ ECOS_VAL_ARM_VFPCOUNT,
+ ECOS_VAL_ARM_CTX_VFPVEC_OFF
+};
+
+struct symbols {
+ const char *name;
+ const char * const *target_names; /* non-NULL when for a specific architecture */
+ bool optional;
+};
+
+#define ECOSSYM(_n, _o, _t) { .name = _n, .optional = (_o), .target_names = _t }
+
+/* Some of offset/size helper symbols are common to all eCos
+ * targets. Unfortunately, for historical reasons, some information is in
+ * architecture specific namespaces leading to some duplication and a larger
+ * vector below. */
+static const struct symbols ecos_symbol_list[] = {
+ ECOSSYM("Cyg_Thread::thread_list", false, NULL),
+ ECOSSYM("Cyg_Scheduler_Base::current_thread", false, NULL),
+ /* Following symbols *are* required for generic application-specific
+ * configuration support, but we mark as optional for backwards
+ * compatibility with the previous fixed Cortex-M3 only RTOS plugin
+ * implementation. */
+ ECOSSYM("__ecospro_syminfo.off.cyg_thread.list_next", true, NULL),
+ ECOSSYM("__ecospro_syminfo.size.cyg_thread.list_next", true, NULL),
+ ECOSSYM("__ecospro_syminfo.off.cyg_thread.state", true, NULL),
+ ECOSSYM("__ecospro_syminfo.size.cyg_thread.state", true, NULL),
+ ECOSSYM("__ecospro_syminfo.off.cyg_thread.sleep_reason", true, NULL),
+ ECOSSYM("__ecospro_syminfo.size.cyg_thread.sleep_reason", true, NULL),
+ ECOSSYM("__ecospro_syminfo.off.cyg_thread.wake_reason", true, NULL),
+ ECOSSYM("__ecospro_syminfo.size.cyg_thread.wake_reason", true, NULL),
+ ECOSSYM("__ecospro_syminfo.off.cyg_thread.unique_id", true, NULL),
+ ECOSSYM("__ecospro_syminfo.size.cyg_thread.unique_id", true, NULL),
+ ECOSSYM("__ecospro_syminfo.off.cyg_thread.name", true, NULL),
+ ECOSSYM("__ecospro_syminfo.size.cyg_thread.name", true, NULL),
+ ECOSSYM("__ecospro_syminfo.off.cyg_thread.priority", true, NULL),
+ ECOSSYM("__ecospro_syminfo.size.cyg_thread.priority", true, NULL),
+ ECOSSYM("__ecospro_syminfo.off.cyg_thread.stack_ptr", true, NULL),
+ ECOSSYM("__ecospro_syminfo.size.cyg_thread.stack_ptr", true, NULL),
+ /* optional Cortex-M: */
+ ECOSSYM("__ecospro_syminfo.cortexm.thread.saved", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.Thread", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.type", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.type", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.basepri", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.basepri", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.sp", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.sp", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.r", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.r", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.pc", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.pc", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.value.HAL_SAVEDREGISTERS.EXCEPTION", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.value.HAL_SAVEDREGISTERS.THREAD", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.value.HAL_SAVEDREGISTERS.INTERRUPT", true, target_cortex_m),
+ /* optional Cortex-M with H/W FPU configured: */
+ ECOSSYM("__ecospro_syminfo.value.HAL_SAVEDREGISTERS.WITH_FPU", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.fpscr", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.fpscr", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.off.HAL_SavedRegisters.u.thread.s", true, target_cortex_m),
+ ECOSSYM("__ecospro_syminfo.size.HAL_SavedRegisters.u.thread.s", true, target_cortex_m),
+ /* optional ARM: */
+ ECOSSYM("ARMREG_SIZE", true, target_arm),
+ ECOSSYM("armreg_r0", true, target_arm),
+ ECOSSYM("armreg_r1", true, target_arm),
+ ECOSSYM("armreg_r2", true, target_arm),
+ ECOSSYM("armreg_r3", true, target_arm),
+ ECOSSYM("armreg_r4", true, target_arm),
+ ECOSSYM("armreg_r5", true, target_arm),
+ ECOSSYM("armreg_r6", true, target_arm),
+ ECOSSYM("armreg_r7", true, target_arm),
+ ECOSSYM("armreg_r8", true, target_arm),
+ ECOSSYM("armreg_r9", true, target_arm),
+ ECOSSYM("armreg_r10", true, target_arm),
+ ECOSSYM("armreg_fp", true, target_arm),
+ ECOSSYM("armreg_ip", true, target_arm),
+ ECOSSYM("armreg_sp", true, target_arm),
+ ECOSSYM("armreg_lr", true, target_arm),
+ ECOSSYM("armreg_pc", true, target_arm),
+ ECOSSYM("armreg_cpsr", true, target_arm),
+ /* optional ARM FPU common: */
+ ECOSSYM("ARMREG_FPUCONTEXT_SIZE", true, target_arm),
+ ECOSSYM("armreg_fpscr", true, target_arm),
+ /* optional ARM FPU single-precision: */
+ ECOSSYM("ARMREG_S_COUNT", true, target_arm),
+ ECOSSYM("armreg_s_vec", true, target_arm),
+ /* optional ARM FPU double-precision: */
+ ECOSSYM("ARMREG_VFP_COUNT", true, target_arm),
+ ECOSSYM("armreg_vfp_vec", true, target_arm),
+};
+
+const struct rtos_type ecos_rtos = {