+#define ECOS_CORTEXM_BASE_NUMREGS (ARMV7M_NUM_CORE_REGS)
+
+/* NOTE: The offsets in this vector are overwritten by the architecture specific
+ * layout functions depending on the specific application configuration. The
+ * ordering of this vector MUST match eCos_reglist. */
+static struct stack_register_offset rtos_ecos_regoff_cortexm[] = {
+ { ARMV7M_R0, -1, 32 }, /* r0 */
+ { ARMV7M_R1, -1, 32 }, /* r1 */
+ { ARMV7M_R2, -1, 32 }, /* r2 */
+ { ARMV7M_R3, -1, 32 }, /* r3 */
+ { ARMV7M_R4, -1, 32 }, /* r4 */
+ { ARMV7M_R5, -1, 32 }, /* r5 */
+ { ARMV7M_R6, -1, 32 }, /* r6 */
+ { ARMV7M_R7, -1, 32 }, /* r7 */
+ { ARMV7M_R8, -1, 32 }, /* r8 */
+ { ARMV7M_R9, -1, 32 }, /* r9 */
+ { ARMV7M_R10, -1, 32 }, /* r10 */
+ { ARMV7M_R11, -1, 32 }, /* r11 */
+ { ARMV7M_R12, -1, 32 }, /* r12 */
+ { ARMV7M_R13, -1, 32 }, /* sp */
+ { ARMV7M_R14, -1, 32 }, /* lr */
+ { ARMV7M_PC, -1, 32 }, /* pc */
+ { ARMV7M_XPSR, -1, 32 }, /* xPSR */
+ { ARMV7M_BASEPRI, -1, 32 }, /* BASEPRI */
+ { ARMV7M_FPSCR, -1, 32 }, /* FPSCR */
+ { ARMV7M_D0, -1, 64 }, /* D0 (S0/S1) */
+ { ARMV7M_D1, -1, 64 }, /* D1 (S2/S3) */
+ { ARMV7M_D2, -1, 64 }, /* D2 (S4/S5) */
+ { ARMV7M_D3, -1, 64 }, /* D3 (S6/S7) */
+ { ARMV7M_D4, -1, 64 }, /* D4 (S8/S9) */
+ { ARMV7M_D5, -1, 64 }, /* D5 (S10/S11) */
+ { ARMV7M_D6, -1, 64 }, /* D6 (S12/S13) */
+ { ARMV7M_D7, -1, 64 }, /* D7 (S14/S15) */
+ { ARMV7M_D8, -1, 64 }, /* D8 (S16/S17) */
+ { ARMV7M_D9, -1, 64 }, /* D9 (S18/S19) */
+ { ARMV7M_D10, -1, 64 }, /* D10 (S20/S21) */
+ { ARMV7M_D11, -1, 64 }, /* D11 (S22/S23) */
+ { ARMV7M_D12, -1, 64 }, /* D12 (S24/S25) */
+ { ARMV7M_D13, -1, 64 }, /* D13 (S26/S27) */
+ { ARMV7M_D14, -1, 64 }, /* D14 (S28/S29) */
+ { ARMV7M_D15, -1, 64 }, /* D15 (S30/S31) */
+};
+
+static struct stack_register_offset rtos_ecos_regoff_arm[] = {
+ { 0, -1, 32 }, /* r0 */
+ { 1, -1, 32 }, /* r1 */
+ { 2, -1, 32 }, /* r2 */
+ { 3, -1, 32 }, /* r3 */
+ { 4, -1, 32 }, /* r4 */
+ { 5, -1, 32 }, /* r5 */
+ { 6, -1, 32 }, /* r6 */
+ { 7, -1, 32 }, /* r7 */
+ { 8, -1, 32 }, /* r8 */
+ { 9, -1, 32 }, /* r9 */
+ { 10, -1, 32 }, /* r10 */
+ { 11, -1, 32 }, /* r11 (fp) */
+ { 12, -1, 32 }, /* r12 (ip) */
+ { 13, -1, 32 }, /* sp (r13) */
+ { 14, -1, 32 }, /* lr (r14) */
+ { 15, -1, 32 }, /* pc (r15) */
+ { 16, -1, 32 }, /* xPSR */
+};
+
+static struct rtos_register_stacking rtos_ecos_stacking = {
+ .stack_registers_size = 0,
+ .stack_growth_direction = -1,
+ .num_output_registers = 0,
+ .calculate_process_stack = NULL, /* stack_alignment */
+ .register_offsets = NULL
+};
+
+/* To avoid the run-time cost of matching explicit symbol names we push the
+ * lookup offsets to this *manually* maintained enumeration which must match the
+ * ecos_symbol_list[] order below. */
+enum ecos_symbol_values {
+ ECOS_VAL_THREAD_LIST = 0,
+ ECOS_VAL_CURRENT_THREAD_PTR,
+ ECOS_VAL_COMMON_THREAD_NEXT_OFF,
+ ECOS_VAL_COMMON_THREAD_NEXT_SIZE,
+ ECOS_VAL_COMMON_THREAD_STATE_OFF,
+ ECOS_VAL_COMMON_THREAD_STATE_SIZE,
+ ECOS_VAL_COMMON_THREAD_SLEEP_OFF,
+ ECOS_VAL_COMMON_THREAD_SLEEP_SIZE,
+ ECOS_VAL_COMMON_THREAD_WAKE_OFF,
+ ECOS_VAL_COMMON_THREAD_WAKE_SIZE,
+ ECOS_VAL_COMMON_THREAD_ID_OFF,
+ ECOS_VAL_COMMON_THREAD_ID_SIZE,
+ ECOS_VAL_COMMON_THREAD_NAME_OFF,
+ ECOS_VAL_COMMON_THREAD_NAME_SIZE,
+ ECOS_VAL_COMMON_THREAD_PRI_OFF,
+ ECOS_VAL_COMMON_THREAD_PRI_SIZE,
+ ECOS_VAL_COMMON_THREAD_STACK_OFF,
+ ECOS_VAL_COMMON_THREAD_STACK_SIZE,
+ ECOS_VAL_CORTEXM_THREAD_SAVED,
+ ECOS_VAL_CORTEXM_CTX_THREAD_SIZE,
+ ECOS_VAL_CORTEXM_CTX_TYPE_OFF,
+ ECOS_VAL_CORTEXM_CTX_TYPE_SIZE,
+ ECOS_VAL_CORTEXM_CTX_BASEPRI_OFF,
+ ECOS_VAL_CORTEXM_CTX_BASEPRI_SIZE,
+ ECOS_VAL_CORTEXM_CTX_SP_OFF,
+ ECOS_VAL_CORTEXM_CTX_SP_SIZE,
+ ECOS_VAL_CORTEXM_CTX_REG_OFF,
+ ECOS_VAL_CORTEXM_CTX_REG_SIZE,
+ ECOS_VAL_CORTEXM_CTX_PC_OFF,
+ ECOS_VAL_CORTEXM_CTX_PC_SIZE,
+ ECOS_VAL_CORTEXM_VAL_EXCEPTION,
+ ECOS_VAL_CORTEXM_VAL_THREAD,
+ ECOS_VAL_CORTEXM_VAL_INTERRUPT,
+ ECOS_VAL_CORTEXM_VAL_FPU,
+ ECOS_VAL_CORTEXM_CTX_FPSCR_OFF,
+ ECOS_VAL_CORTEXM_CTX_FPSCR_SIZE,
+ ECOS_VAL_CORTEXM_CTX_S_OFF,
+ ECOS_VAL_CORTEXM_CTX_S_SIZE,
+ ECOS_VAL_ARM_REGSIZE,
+ ECOS_VAL_ARM_CTX_R0_OFF,
+ ECOS_VAL_ARM_CTX_R1_OFF,
+ ECOS_VAL_ARM_CTX_R2_OFF,
+ ECOS_VAL_ARM_CTX_R3_OFF,
+ ECOS_VAL_ARM_CTX_R4_OFF,
+ ECOS_VAL_ARM_CTX_R5_OFF,
+ ECOS_VAL_ARM_CTX_R6_OFF,
+ ECOS_VAL_ARM_CTX_R7_OFF,
+ ECOS_VAL_ARM_CTX_R8_OFF,
+ ECOS_VAL_ARM_CTX_R9_OFF,
+ ECOS_VAL_ARM_CTX_R10_OFF,
+ ECOS_VAL_ARM_CTX_FP_OFF,
+ ECOS_VAL_ARM_CTX_IP_OFF,
+ ECOS_VAL_ARM_CTX_SP_OFF,
+ ECOS_VAL_ARM_CTX_LR_OFF,
+ ECOS_VAL_ARM_CTX_PC_OFF,
+ ECOS_VAL_ARM_CTX_CPSR_OFF,
+ ECOS_VAL_ARM_FPUSIZE,
+ ECOS_VAL_ARM_CTX_FPSCR_OFF,
+ ECOS_VAL_ARM_SCOUNT,
+ ECOS_VAL_ARM_CTX_SVEC_OFF,
+ ECOS_VAL_ARM_VFPCOUNT,
+ ECOS_VAL_ARM_CTX_VFPVEC_OFF