+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2017 by Intel Corporation
* Leandro Pereira <leandro.pereira@intel.com>
* Daniel Glöckner <dg@emlix.com>*
* Copyright (C) 2021 by Synopsys, Inc.
* Evgeniy Didin <didin@synopsys.com>
- * *
- * SPDX-License-Identifier: GPL-2.0-or-later *
***************************************************************************/
#ifdef HAVE_CONFIG_H
OFFSET_T_ARCH,
OFFSET_T_PREEMPT_FLOAT,
OFFSET_T_COOP_FLOAT,
+ OFFSET_T_ARM_EXC_RETURN,
OFFSET_MAX
};
{ ARMV7M_R13, -2, 32 },
{ ARMV7M_R14, 20, 32 },
{ ARMV7M_PC, 24, 32 },
- { ARMV7M_xPSR, 28, 32 },
+ { ARMV7M_XPSR, 28, 32 },
};
static struct stack_register_offset arc_cpu_saved[] = {
ZEPHYR_VAL_COUNT
};
-static int64_t zephyr_cortex_m_stack_align(struct target *target,
+static target_addr_t zephyr_cortex_m_stack_align(struct target *target,
const uint8_t *stack_data,
- const struct rtos_register_stacking *stacking, int64_t stack_ptr)
+ const struct rtos_register_stacking *stacking, target_addr_t stack_ptr)
{
return rtos_cortex_m_stack_align(target, stack_data, stacking,
stack_ptr, ARM_XPSR_OFFSET);
.optional = false
},
{
- .symbol_name = "_kernel_openocd_offsets",
+ .symbol_name = "_kernel_thread_info_offsets",
.optional = false
},
{
- .symbol_name = "_kernel_openocd_size_t_size",
+ .symbol_name = "_kernel_thread_info_size_t_size",
.optional = false
},
{
- .symbol_name = "_kernel_openocd_num_offsets",
+ .symbol_name = "_kernel_thread_info_num_offsets",
.optional = true
},
{
return ERROR_OK;
}
-struct rtos_type zephyr_rtos = {
+const struct rtos_type zephyr_rtos = {
.name = "Zephyr",
.detect_rtos = zephyr_detect_rtos,